Something from the "What I found" section. This is 74LS74 flip flop internal schematic.
The 74F74 looks very similar. Here the internal circuit of a 74F00:
Main differences are slight changes to the output stage that speed up the output stage, resistor values in the rest of the circuit.
While not on the same level in terms of freedom of noise etc, as ECL, it's pretty decent.
We will see some current dependent on the actual clock that drives the clock input, around (~ 0.38mA @ 5V) internal and a similar current via the the input circuit.
Data related current changes should be minimal, it looks kinda like a see-saw due to the balanced circuit, the rest is all balanced.
The totem pole outputs in 74F circuits are especially concerned with avoiding shoot through current, so these should be pretty clean too.
Hence using 74F74 for reclocking, we should use the lowest reclocking frequency usable (same of course applies for anything except ECL), decouple the power supplies primarily for this frequency and harmonics.
The "flying attenuator & slew rate limiter" sit between the two outputs and are pretty high impedance, so they do not effect the current flows. If we place the attenuators directly at the IC, there is no extra capacitive load to drive, which thus doesn't causes charge/discharge current spikes in the supply/gnd lines.
E.g. if we allow 384kHz max Fs with 6.144 MHz BCK, using 12.288MHz for reclocking BCK, DL, DR is the lowest frequency possible.
Take account that data lines change on the rising BCK edge but is latched, bit by bit on the falling edge of BCK.
So with 22.../24... MHz MCK we divide by 2 and latch BCK and Data reclockers on opposite edges. We can likely divide reclocked BCK more to reclock LE and generate FDEM.
Thor
The 74F74 looks very similar. Here the internal circuit of a 74F00:
Main differences are slight changes to the output stage that speed up the output stage, resistor values in the rest of the circuit.
While not on the same level in terms of freedom of noise etc, as ECL, it's pretty decent.
We will see some current dependent on the actual clock that drives the clock input, around (~ 0.38mA @ 5V) internal and a similar current via the the input circuit.
Data related current changes should be minimal, it looks kinda like a see-saw due to the balanced circuit, the rest is all balanced.
The totem pole outputs in 74F circuits are especially concerned with avoiding shoot through current, so these should be pretty clean too.
Hence using 74F74 for reclocking, we should use the lowest reclocking frequency usable (same of course applies for anything except ECL), decouple the power supplies primarily for this frequency and harmonics.
The "flying attenuator & slew rate limiter" sit between the two outputs and are pretty high impedance, so they do not effect the current flows. If we place the attenuators directly at the IC, there is no extra capacitive load to drive, which thus doesn't causes charge/discharge current spikes in the supply/gnd lines.
E.g. if we allow 384kHz max Fs with 6.144 MHz BCK, using 12.288MHz for reclocking BCK, DL, DR is the lowest frequency possible.
Take account that data lines change on the rising BCK edge but is latched, bit by bit on the falling edge of BCK.
So with 22.../24... MHz MCK we divide by 2 and latch BCK and Data reclockers on opposite edges. We can likely divide reclocked BCK more to reclock LE and generate FDEM.
Thor
Last edited:
Hi Thorsten, first off thanks for taking the time to respond, as mentioned worst case I'm learning a few things, and in the process hopefully not wasting too much of the more knowledgable crowd's time, if so my apologies and free to tell me (I'm Dutch I can have it 😀)
But perhaps I'm brainwashed by marketing too much and their praise of dual mono, mono block amps etc.. but perhaps I'm finally coming full circle by trying things myself en being enlightened by diyaudio.com 🙂
Anyway of my above reasoning might be incorrect, or the effect of it so small that it's like you advice not worth the trouble and using a proper power supply be much more important than paralleling chips or running them in balanced mode.
For now I'll go back to my humble spot at the bottom of diyaudio ladder of wisdom and let you guys go on with all the amazing stuff you are developing! Again thanks for the replies, I do appreciate!
You could reverse the argument, at such low channel separation, you want to maintain as much of this as possible one cannot re-separate mixed signals. The other benefit I could see is that if on the left channel there is a large draw from the power supply, and the right channel has a much smaller demand, the left channel cannot negatively affect the right channel and vice versa.
But perhaps I'm brainwashed by marketing too much and their praise of dual mono, mono block amps etc.. but perhaps I'm finally coming full circle by trying things myself en being enlightened by diyaudio.com 🙂
I'm thinking noise from the power supplies, data lines, clocks and internal noise of the chip (although the latter might not necessarily be symmetric between the two outputs and thus not cancel out).
My understanding of the 0 crossing, but I'm happy to to stand corrected, is that almost all bits switch at the same time. This would draw a lot of current and could potentially cause a 'dip' in the output. If this dip happens on both sides it would cancel out. Now at the risk of contradicting my own reasoning, the issue might be more nuanced and lead to other probably more nast non symmetric issues. However, these could potentially still be in the same ratio to the output signal as you have twice the signal.
Anyway of my above reasoning might be incorrect, or the effect of it so small that it's like you advice not worth the trouble and using a proper power supply be much more important than paralleling chips or running them in balanced mode.
Perhaps in a far future I'm advanced enough to embark on such an ambitious journey 🙂
For now I'll go back to my humble spot at the bottom of diyaudio ladder of wisdom and let you guys go on with all the amazing stuff you are developing! Again thanks for the replies, I do appreciate!
I am not seeing how this is a valid argument. You want enough channel separation to not degrade what you get from the recording materially, but that's not all that much.
Most low level circuits operate in Class for reasonable signals.
The TDA1541 especially is very much a "Class A" design.
Classic haai eend.
The TDA1541 itself has quite PSRR, you need a LOT of power supply noise to get something material.
Yup, it doesn't cancel well and the frequencies are quite high, making any cancellation even more challenging.
Balanced circuits typically have a falling rejection of common mode noise with frequency. They are really good at rejecting low frequency common mode noise, say from mains power, fundamental and the first few harmonics. The rest, not so much.
Correct.
Why would that draw "a lot of current"? What is a lot?
ONLY if the "dip" or glitch, as it is more commonly known is in the same polarity AND slow enough to be rejected by normal circuitry.
Now first, as for balanced we invert the signal in the digital domain , we actually have 1LSB offset and the two DAC's create their glitch at 1LSB apart. Secondly, the first DAC will switch from 0x0000 to 0x8000 and the other from 0x8000 to 0x0000.
So not will the two glitches not be simultaneous, they will also be opposite polarity and thus add, not subtract.
Nope, instead learn and go up. Rapidly.
Key is to abandon "magical thinking".
And to avoid to fool ourselves, both into hearing non-existent differences and into not hearing differences that exist:
https://tu-dresden.de/mn/psychologie/ifap/kknw/die-professur/news/we-hear-what-we-expect-to-hear
Thor
My ambition! Thanks for all the insights, I might just have climbed a step on that ladder, now back to the soldering iron 🙂 Thanks!
I measured very similar THD. It seems one either needs a big core with many turns or some other trick to achive low THD at the bottom frequency range. The best I could get is 1% at 40 Hz 0 dBu, 0.004% at 1 kHz (acceptable) 20-30-40 kHz is no problem.
Correct.
Zero Field.
Not enough turns. Try 10X. And yes, that is extremely thin secondary wire, many turns and layers to get good results.
Thor
Has anyone checked if masterclock works on pin H3.5 or pin H3.7 of the JLsounds I2SoverUSB v.III board when it is configured for simultaneous mode?
(I mean the older v.III version, not the newer Fully Isolated Output version)
I wasn't aware of two versions of the V.III until reading your post.
What is the difference here? On both descriptions I can read:
Galvanic isolation (outputs, two oscillators and reclock, done by Xilinx
CPLD are after the isolator)
Again, on both one finds in the PDF "Bus-powered USB side and external power supply for oscillators and reclock.In this case there is galvanic isolation between the USB side and userapplication side. Plug the USB cable to USB B connector, provide externalpower supply to H3.17 and H3.19 (4.5V to 5.3V). Consumption from USB hostis less than 400mA, consumption from external power supply for oscillators andreclock is less than 100mA."
What is the difference?
BTW, Lyuben told me some years ago the was working in a multichannel version, but that has not not shown up in his website. Anybody aware of any better multichannel USB to I2S solution than the one from diyinhk (I beleive that is their last version)?
I just quickly checked your thread. Interesting, specially if you keep/develop isolation and external clocks. I would suggest not to try to save your clients a few EUR (like you mentioned in one of the last posts in your thread) but instead to try offer something that can play at JLsounds level with multichannel capability. There are already cheap boards out there.
For us using diy DACs a very high quality multichannel solution is non existent (to my knowledge) and the digital XO/multiamp route could be worth trying out.
Gentlemen:
This is already a very long thread.
Please do not post anything not relating directly to TDA1541.
This is already a very long thread.
Please do not post anything not relating directly to TDA1541.
Very interesting. So the balanced setup with one TDA1541 per channel is out! Unless you use a FPGA to make the logic to correct this.
It actually makes 100% sense to me. I've tried balanced setups with a few old school DACs and wasn't happy with the results. I posted my impressions in this thread a while ago.
It is not about the area of core. You dont need the power... It is about permeability of core.
And the inductance of primary.
.
if it is core area increased, the lenght of the turn is also incresaed and Rcd of all turns will be significantly larger.
.
Simulate or calculate the needed value of primary inductance, with respect to input source impedance, but with minimum phase shift...
So the minimum phase shift is about +5 to +8 deg at 20Hz. That will end up with lower -3db point most probably lower than 10Hz...
And increased primary inductance.
.
I tried TDA1541A (one chip L/-L channel) and TDA1540 (2 chips) in balanced mode (with inverted DATA line) in Time Simoultaneous format.
I was not listening a lot, but I didnt note any deviations against the standard configuration?
Unfortunatley I didnt masure anything and it was fast test... Sorry i sould...
My target is 10 Hz lower cutoff frequency, where the T time constant is 16 ms. If the I/V resistor is 33R, then from T=L/R I got Lp=0.5 Henry. And with 1:15 turns ratio Ls=120 Henry.
The problem is to keep both B field and Rdc very low. This is why we need a bigger core with more turns and thick wire.
I think the requirements are different than for a moving coil transformer, where there are lower currents and lower voltages. MC transformers can be small.
Post DAC stages should approximate cumulative THD+N around 0.0003% at 0dBF ~110dB across the audio pass-band to guarantee 16 bit res.
It is VERY difficult/elaborative/expensive to achieve this with transformers at lower band of spectrum.
Ofcourse one has the choice of neglecting this . . . . Many designs do.☹
TDA1541A is such an incredible sounding DAC that it would be a shame to throw away resolution.
Cheers
It is VERY difficult/elaborative/expensive to achieve this with transformers at lower band of spectrum.
Ofcourse one has the choice of neglecting this . . . . Many designs do.☹
TDA1541A is such an incredible sounding DAC that it would be a shame to throw away resolution.
Cheers
Last edited:
Yes, but you need still need to handle the flux.
"Magnetic flux is inversely proportional to frequency, meaning that as frequency increases, magnetic flux decrease"
Low distortion at low frequencies = (relatively) large core
And flux, which doubles with halving frequency.
You see that here, above where hysteresis/barkhausen screws up the relationship, a near straight line of HD increasing with lowering frequency because flux in the core increases. Once you get to high enough levels the relation between increase in level (flux) and HD for a fixed frequency is also pretty linear.
Of course. You have a choice between more turns on the same core (less flux) and a larger core with the same turns (less flux) to lower LF distortion. Again, to the best of my knowledge this is independent from the specific core alloy/material is used. How far we deviate from this ideal at low and high levels does depend on the core material.
Audio transformers are a great illustration of TANSTAAFL.
Thor