I'm sure you was ! I am green country side pilgrimming next week but still connected, but no mobile workshop, ahaha !
Ciao, good holyday to you and to you all if having some.
Ciao, good holyday to you and to you all if having some.
hum forget the agnd to dgnd ic pins to planes conection I asked above in order to make it quiter between digital and analog part of the dac chip.
It's HF so it's obvious the current flows through the least impedance/inductance path, so will spread to the most adjacent layer of the digital pin connected plane.
Maybe better just to connect each pin where it belongs directly 3D (back to back diodes or wire if used between them, tht cap 3D connection above the ic (antenna?)) if at the next power pin of the ic. Illustration: DGND to 5V with a cap.
I was naivly thinking enlarging the loop between the two pins will lower the stray capacitance and also because the added inductance (despite being low cause one plain layer used just for each pin before they meet to the starground for the classic method with as last layer of the star ground vias a plain Vref layer) acheives some filtering of HF digital towards the AGND pin. But it would just enlarge the loop. So better to connect them near the "true" Ref (-15V/+5V...).
Questions of agnd/dgnd pins has been solved in the other long thread (posts of Thorsten and Zoran)
It's HF so it's obvious the current flows through the least impedance/inductance path, so will spread to the most adjacent layer of the digital pin connected plane.
Maybe better just to connect each pin where it belongs directly 3D (back to back diodes or wire if used between them, tht cap 3D connection above the ic (antenna?)) if at the next power pin of the ic. Illustration: DGND to 5V with a cap.
I was naivly thinking enlarging the loop between the two pins will lower the stray capacitance and also because the added inductance (despite being low cause one plain layer used just for each pin before they meet to the starground for the classic method with as last layer of the star ground vias a plain Vref layer) acheives some filtering of HF digital towards the AGND pin. But it would just enlarge the loop. So better to connect them near the "true" Ref (-15V/+5V...).
Questions of agnd/dgnd pins has been solved in the other long thread (posts of Thorsten and Zoran)
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No surmising Iggy just for experience sake try out 25 vs 50v KZ. For 1 moment leave the inductance etc thoughts out & give it a gd listen.
big surprise ya. Specs are just specs you should know better. Oh dont remove the 0.1 uf pps caps.
Cheers
bad idea not to remove it ! No 50 hz for me until a board with a corect layout, not my priority yet.
I do not like ceramic, but wonder if some "no flex" treated amagnetic X7R will works (TDK ?) ? in lieu of the UKLs for you (in spite of the 0.1 PPS), what value and cap stylle do you use btw for the DEM C. (between pin 16/17) ?
I do not like ceramic, but wonder if some "no flex" treated amagnetic X7R will works (TDK ?) ? in lieu of the UKLs for you (in spite of the 0.1 PPS), what value and cap stylle do you use btw for the DEM C. (between pin 16/17) ?
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Philips grading process at manufacturing is described here:
https://www.dutchaudioclassics.nl/Grading_process_of_the_Philips_TDA1541A_R1_S1/
I still don't know where the S2 aka "double crown" came from.
https://www.dutchaudioclassics.nl/Grading_process_of_the_Philips_TDA1541A_R1_S1/
I still don't know where the S2 aka "double crown" came from.
Nah, use C0G for ceramics. You can easily place 0.1uF (or even 10nF) C0G SMD capacitors below the TDA1541 to -15V to deal with the VHF disturbance's on the DEM Filter pins.
Thor
Alas, lcsaszar measured the actual currents and showed my analysis to be incorrect.
So everything is back "wide open". And I was wrong.
Thor
no more -15V main decoupling ?! I still do wonder why the 14 DEM were going Back to the Agnd pin in the orthodoxal canon ? If not -15V then they should be see the DGND pin 14 first ? How funny, 14 DEM caps to Pin 14 ! Philips Easter Egg ! Then AGND and DGND layers only met near the PS with the two piggy backed diode ?
It is possible the shematic of the Guy you worked on is non accurate ! Alas the Philips scanned paper sheets are not going back to the surface !
A britanic gentleman I advised by PM after he asked me, tried the acrylic decoupling VS Pan PPS and liked it better. Acrylic in Cornel Dublier paper about his FCA caps (soon NLA) shows the same behavior than Ceramic Class I . But still, after all the circuitries after, ears seems to makes the difference between two different dielectrics... Which I am the first to find odd ! Maybe also the acrylic smd caps have a variation of capacitance during soldering hand process because too much heat ? It's relative fragile caps, that are already from the fab to be made precise... The acrylic from Rubycon seems less fragile, but expensive and not sure the datasheets have the same max second/temp soldering limits too. It's like polystyren caps... fragiles !
Stupid question, i appologize : The 3 voltages rail are DC at the pins 28/26/15 ? DC flows towards positive poles ?
At 14 Dem 14 caps and DGND, it is AC ? currents are changing direction and where that flows inside and outsiide the PCB is more complex to measure ?
Is a static measurement of the TDA1541A about currentis the same than when the IC is modulated with a signal trough the I2S inputs (or Sim) ?
How to see where the current is flowing back from the next device ? simply measuring the DC at power pins of the TDA1541A ?
With 2 mA at pin 5, there is a chance tha AGND layer should stay clean around the TDA1541A pins and maybe the AoL/R traces to be sandwiched between the Agnd and Dgnd layer ? Maybe simply going back to pin 6 and pin 25 if a layer is at their vinicity ?
It is possible the shematic of the Guy you worked on is non accurate ! Alas the Philips scanned paper sheets are not going back to the surface !
A britanic gentleman I advised by PM after he asked me, tried the acrylic decoupling VS Pan PPS and liked it better. Acrylic in Cornel Dublier paper about his FCA caps (soon NLA) shows the same behavior than Ceramic Class I . But still, after all the circuitries after, ears seems to makes the difference between two different dielectrics... Which I am the first to find odd ! Maybe also the acrylic smd caps have a variation of capacitance during soldering hand process because too much heat ? It's relative fragile caps, that are already from the fab to be made precise... The acrylic from Rubycon seems less fragile, but expensive and not sure the datasheets have the same max second/temp soldering limits too. It's like polystyren caps... fragiles !
Stupid question, i appologize : The 3 voltages rail are DC at the pins 28/26/15 ? DC flows towards positive poles ?
At 14 Dem 14 caps and DGND, it is AC ? currents are changing direction and where that flows inside and outsiide the PCB is more complex to measure ?
Is a static measurement of the TDA1541A about currentis the same than when the IC is modulated with a signal trough the I2S inputs (or Sim) ?
How to see where the current is flowing back from the next device ? simply measuring the DC at power pins of the TDA1541A ?
With 2 mA at pin 5, there is a chance tha AGND layer should stay clean around the TDA1541A pins and maybe the AoL/R traces to be sandwiched between the Agnd and Dgnd layer ? Maybe simply going back to pin 6 and pin 25 if a layer is at their vinicity ?
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Edit : answered here : https://www.diyaudio.com/community/...ate-nos-dac-using-tda1541a.79452/post-7808497
No, that stays. Only the separation between AGND and DGND is affected.
Yes, so I really appreciate @lcsaszar work.It removes a lot of guesswork.
Doubtful. In mass production I have used both Panasonic and CDE acrylic SMD caps interchangeable, whichever one was in stock was ordered when it was order time. Never noticed a difference, measurements or listening.
Yes.
Strictly speaking yes. Current, that is electrons for a surplus at the (-) pole and flow towards (+).
AC and still -15V.
Largely yes.
No. Think how the current loops form.
It's important not confuse or comingle AC-DC...
Thor
Attached photos from the oscilloscope screen, bit transitions visualized.
0111...1111
1000...0000
1000...0001
0111...1111
1000...0000
1000...0001
Attachments
I guess somehow the bit transition "down" is messed up, but why?
And is this one IC (possibly out of normal spec) or architecture specific?
Do you know this:
Nakamichi has a patent on this.
Thor
Sure. This is for Wemos D1 mini, an ESP8266 variant. I will port it to ESP32 because it has more memory.