I measured the leakage current of Nichicon Muse UKZ (black with golden letters) 100 uF/25 V after 1 day formatting. It was between 1 and 10 Gohm. UKL is even better. Compare it to 10 Mohm that I used, the leakage of this capacitor is 1/100 to 1/1000 less, I think it causes negligible DNL error.
Measuring tool was a Radiometer IM-6 Megohmmeter, it can measure down to 1 pA or up to 10^9 Mohm.
Measuring tool was a Radiometer IM-6 Megohmmeter, it can measure down to 1 pA or up to 10^9 Mohm.
Here is an 1/2 LSB DNL @ bit #10, and the resulting spectrum. Left channel, 0.3% THD. The step signal is 12 samples 0x03FF, followed by 24 samples 0x0400, followed by 12 samples 0x0401. That is 1 LSB change around Bit #10. 1 LSB is 2 vertical grid.
I misadjusted the compensation so that Bit #10 is 1/2 LSB less (1 grid instead of 2) than the cumulative Bit #0 to Bit #9 (they are all 1s, then they change to all 0s and Bit #10 turns to 1, that is the 24 samples plateau). The spectrum is again the 6 least significant bits holding dithered 400 Hz sine, shifted by Bit #10 DC level.
Right channel is OK without compensation.
I misadjusted the compensation so that Bit #10 is 1/2 LSB less (1 grid instead of 2) than the cumulative Bit #0 to Bit #9 (they are all 1s, then they change to all 0s and Bit #10 turns to 1, that is the 24 samples plateau). The spectrum is again the 6 least significant bits holding dithered 400 Hz sine, shifted by Bit #10 DC level.
Right channel is OK without compensation.
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Hi, the leakage should be very close what he measured for the other UKZ. Most difference between the 3 voltage familly is the angle of tangeant loss, then inductance due to the different leads spacing and form factor & casing due to the voltages ratings.
It is set by the Test Voltage, i.e. 15 V.
Wrong , UKZ 100 uf 25 v has 25 uA leakage , UKZ 100 uf 50 v has 50 uA leakage
as we all know , only the UKL 100 uf 25 v has leakage ( in the real world ) low enought to work well with the DEM 50 Hz
I have tried some caps https://www.mouser.fr/ProductDetail/710-865090445008 having the same ( datasheet ) leakage as the UKL ( 5 uA ) , and the result was 10/15 db worst all the way 😒
For your information Kemetic T489 serie have leakage way off the needs
our chance is that the UKL have specs in the real world way better than datasheet says 😎
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uH show, the measurements, I disagree. You are not We. And proves you hear it (over the bad layout of your pcb as far I can judge by what you posted, sorry no personnal attack, but just the work I find no a real progress)?!
Ofcourse UKL are better for that than UKZ, no need to invent powder to know that,just read the datasheets about leakage ! What I highligth is you need to corelate it wit listening test. This DEM is not the end of the world as far it is to makesounds good the TDA1541A,but if you battle on numbers only and discuss about the last outrage made to a drosophile. (you can do it, I hate tiger mosquitoes 😉 )
As with the DEM 50 Hz and the double TDA1541A, I disagree, but hey it is a free world and it is ok if we disagree (multiple blink eyes, etc) 🙂
Yeah thanks for the T489, I was not sure it was low enough for this DEM needs in real world ears test benchmark. You certainly tried it already.
Ofcourse UKL are better for that than UKZ, no need to invent powder to know that,just read the datasheets about leakage ! What I highligth is you need to corelate it wit listening test. This DEM is not the end of the world as far it is to makesounds good the TDA1541A,but if you battle on numbers only and discuss about the last outrage made to a drosophile. (you can do it, I hate tiger mosquitoes 😉 )
As with the DEM 50 Hz and the double TDA1541A, I disagree, but hey it is a free world and it is ok if we disagree (multiple blink eyes, etc) 🙂
Yeah thanks for the T489, I was not sure it was low enough for this DEM needs in real world ears test benchmark. You certainly tried it already.
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Putting aside leakage pls test & listen to UKZ 100uf 50v & share with us your thoughts.
Moderation team
Leakage current can be nulled out with the compensation method that is subject of this thread. 😉 Please focus on it instead of capacitor particulars.
UKZ 100 uF/25 V. Nearly 10 Gohm, let's estimate 7.5 Gohm. Bigger size than UFG (not UKG, it' a typo). 15 V / 7.5 Gohm = 2 nA.
There might be sonic differences, but I don't think it is due to leakage caused DNL. In any case, if in doubt, a film capacitor is a safe choice.
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This is the compensation circuit. I measured the THD at Bit #10 and Bit #11 and found that the compensation did not bring much benefit (just like at Bit #9), so I omitted that part.
How to use it?
Send an I2S data stream that represents a -60 dBFS sine, dithered with triangular probability density function of 2 LSB, digitally shifted according to the bit to be compensated. For example, at Bit #12 add 0x1000, Bit #13 0x2000, Bit #14 0x4000, Bit #15 0x8000.
Measure the analog output of the DAC with an FFT analyzer. You will see the fundamental and the 2nd (and 3rd, etc.) harmonics.
Connect the compensation circuit to pin 10/21 (Bit #12) only. Dial in the lowest 2nd harmonic, it should disappear in the noise.
Next connect the compensation circuit to pin 11/20 (Bit #13), leave also Bit #12. Find lowest 2nd harmonic.
Do the same for pin 12/19 (Bit #14), leave the previous bits untouched.
Finally connect pin 13/18 (MSB, Bit #15), compensate for lowest THD.
I used removable jumpers for connection the relevant pins, starting from Bit #12, always adding the next pin and compensating, ending with all four jumper set, finishing with Bit #15.
Creating I2S data stream
It can be generated with any USB/I2S device and e.g. Audacity, but I am not sure if the digital shift can be provisioned this way. Without digital shift you can compensate around analog zero crossing only, that is Bit#15 (when Bit #15 changes from 0x7FFF to 0x8000). I built a simple I2S generator for the purpose.
How to use it?
Send an I2S data stream that represents a -60 dBFS sine, dithered with triangular probability density function of 2 LSB, digitally shifted according to the bit to be compensated. For example, at Bit #12 add 0x1000, Bit #13 0x2000, Bit #14 0x4000, Bit #15 0x8000.
Measure the analog output of the DAC with an FFT analyzer. You will see the fundamental and the 2nd (and 3rd, etc.) harmonics.
Connect the compensation circuit to pin 10/21 (Bit #12) only. Dial in the lowest 2nd harmonic, it should disappear in the noise.
Next connect the compensation circuit to pin 11/20 (Bit #13), leave also Bit #12. Find lowest 2nd harmonic.
Do the same for pin 12/19 (Bit #14), leave the previous bits untouched.
Finally connect pin 13/18 (MSB, Bit #15), compensate for lowest THD.
I used removable jumpers for connection the relevant pins, starting from Bit #12, always adding the next pin and compensating, ending with all four jumper set, finishing with Bit #15.
Creating I2S data stream
It can be generated with any USB/I2S device and e.g. Audacity, but I am not sure if the digital shift can be provisioned this way. Without digital shift you can compensate around analog zero crossing only, that is Bit#15 (when Bit #15 changes from 0x7FFF to 0x8000). I built a simple I2S generator for the purpose.
Cermet wont work for the job , I have use them for the 2 mA biais at the TDA output , result is not very stable , the one who would work are the Vishay 1280 G series but they come at 30/40 euro each , you'd better fit some UKL caps on your board , as you said before they have negligible DNL error
not to mention the cost of the 8 highly stable résistors you need
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not to mention the cost of the 8 highly stable résistors you need
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Thanks for the advice on the trimmer choice.
The point is that DNL is not due to capacitor leakage (if it is, the capacitor is really bad) but due to the TDA manufacturing process. Imperfect current division /2 in the successive stages is the cause of it. The wafers are measured by a multi-pin test tool. The out-of spec wafers are discarded, the rest is graded R1, standard and S1. This grading is based on the DNL.
The good news is that the DNL can be perfectly nulled out. Essentially we can upgrade the chip to a higher grade.
The point is that DNL is not due to capacitor leakage (if it is, the capacitor is really bad) but due to the TDA manufacturing process. Imperfect current division /2 in the successive stages is the cause of it. The wafers are measured by a multi-pin test tool. The out-of spec wafers are discarded, the rest is graded R1, standard and S1. This grading is based on the DNL.
The good news is that the DNL can be perfectly nulled out. Essentially we can upgrade the chip to a higher grade.