Bipolar discrete shunt regulators

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#182
Re: corrected version

MRupp said:
Here is my corrected and final version, with the cascoded current source as I would implement it, but I am off course not the owner of this project. R5 is still left in to allow higher voltages than J3 can take. Do not get too hung up on the particular JFets, bjts, and resistor values, there is still some room to tweak, e.g. if a particular part cannot be obtained:
Click to expand...


Martin,

Please put your LTSpice model up for download.

Thanks
Jim
 
#184
Only comment I have is to connect bottom of R2 to emitter Q3 instead of to ground.
Click to expand...

Changed, and Netlist added:
 

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#186
Next step would be to replace this R with a ccs.
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"In my simulations" - ideal CCS at 8mA - this does not change the PSRR, and improves the output impedance very slightly, less then 1 dB. But either the models suck or I am not testing the output impedance correctly, or it really does not do much.
 
#187
MRupp said:


"In my simulations" - ideal CCS at 8mA - this does not change the PSRR, and improves the output impedance very slightly, less then 1 dB. But either the models suck or I am not testing the output impedance correctly, or it really does not do much.
Click to expand...

Martin,

It will have more impact with low Vout, like +5V reg. Then, R2 gets much lower and acts less and less as a CCS.
Can you look at that in your sim?

Jan Didden
 
#188
I changed the regulator to 6 Volts, replaced D4, D5 with a Diode, the Zener with a LED, to have some voltage margin for Q3. For a 5V version I think infrared LEDs (1.2 Volts) might be in order, I hope this is good enough for now (?):
 

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#190
Here is the graph showing output ripple suppression, if that is the right word. I set the AC load to 50mA standing current and 5mA AC current, Vin is now 12V AC 0V DC. The curve looks strikingly similar to the first, so maybe I am not measuring the right thing ?
 

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#191
Another suggestion: what would happen if we move D1/D3 current sink from ground and tied it to regulator output? We could change it to the simple one J-fet CCS, and I think the current loop would be shorter? Could we face some regulator start up problem if we do so?
 
#193
aparatusonitus said:
Another suggestion: what would happen if we move D1/D3 current sink from ground and tied it to regulator output? We could change it to the simple one J-fet CCS, and I think the current loop would be shorter? Could we face some regulator start up problem if we do so?
Click to expand...


The current through D1/D3 contains (a lot of) ripple current. You would be injecting it into the output. I can see only disadvantages.

Jan Didden
 
#194
Here the last suggestion, looks much worse, curve in red.

Martin you mean Vin = 12V DC and 0V AC?
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Jan, for the first diagram (PSRR) I set Vin 12 V DC and 1 V AC, for the second diagram I added 5mA AC load current (output load I1 and 2, both already set to 50 mA DC current) and changed the Vin AC component to 0 Volts, not that it did change the curve in any way but I thought this might be a cleaner cut between the two situations. Hope this answers it ? I just wonder if there is another way to measure these values.
 

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#196
MRupp said:
Here the last suggestion, looks much worse, curve in red.



Jan, for the first diagram (PSRR) I set Vin 12 V DC and 1 V AC, for the second diagram I added 5mA AC load current (output load I1 and 2, both already set to 50 mA DC current) and changed the Vin AC component to 0 Volts, not that it did change the curve in any way but I thought this might be a cleaner cut between the two situations. Hope this answers it ? I just wonder if there is another way to measure these values.
Click to expand...


No you measure OK, but in your earlier post you said "Vin to 12V AC and 0V DC", I thought that was a typo and you confirmed that.

I guess in both cases you measure at Vout, of course.

Now, why would the curves swing up after 20kHz or so? Not a big issue, just wondering.

Jan Didden
 
#197
Only saw my typo after the reply.

Would you be so kind to simulate up to MHZ range so we can see what goes there. Can we include at the input some ferrite or small inductor (100u to 1mH) to improve high frequency behaviour?
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I am stealing my time from somewhere else and cannot do more sims right now. You have the netlist and are welcome to try yourself. The frequency limit was set to better show the differences at low frequencees, they even out in the MHz range, basically you have the upward slope into the 10s of MHz. I inserted a 1 mH / 5 Ohms inductor after the CCS and before the actual shuntreg. It does indeed improve PSRR as expected but shows a resonance peak. So yes, can be done but we need to look into damping this. Suggestions are welcome.
 
#200
I agree, get rid of the ground plane.
Use a star connected ground point that coincides with the output ground.
And make sure that the output live is also a star connected point that coincides with the output live. As an example look at the route from LED1 to the output, how many other devices are sharing that trace?
The sense traces leads could be done as links and that leaves the option to take the sense leads to a very close load PCB (one stacked above the other).
 
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