I have been playing around with regulators in LTSpice, trying to come up with something I like for use with a DAC I am working on. The regulators shown are what I am currently intending to use to power the discrete I/V and output buffer stage. I will also most likely adapt this for powering the 3.3v and 5v digital supplies.
I/V topology it is intended for is folded cascode class A, so has constant power draw, and requires +/-15vdc rails between 40-50mA per channel, depending on the variation I use. I prefer, at least conceptually, to use shunt regulators when possible, so worked on coming up with some possibilities. The one below is what I think I am going to go with. Not the absolute best performance possible, but I think it should be more than sufficient for my needs.
The minor parts variations between the two circuits, besides those obviously directly caused by changing polarity, are to balance performance. It seems the only truly important parts are the two compensation capacitor values. Hopefully my old *** 20MHz DSO will be up to the task of finding real world values. Of the various transistor models I tried, it is ironic that the best performance seems to come from the ones I have most of in my parts bin.
Rising impedance at HF can be tamed with ~6.8uf of capacitance on the output, though you have to be careful with the ESR of the capacitor. Reduction in ripple rejection at HF can most easily be tamed by a small CLC filter before the regulator. A 1uf, 1uh 1ohm, 1uf pi filter knocks the heck out of the noise at HF, rolling it off past about 10KHz.
Remember that all of these values are simulator values, and my skill with simulation is sorely lacking, so take everything here with a shaker of salt.
I/V topology it is intended for is folded cascode class A, so has constant power draw, and requires +/-15vdc rails between 40-50mA per channel, depending on the variation I use. I prefer, at least conceptually, to use shunt regulators when possible, so worked on coming up with some possibilities. The one below is what I think I am going to go with. Not the absolute best performance possible, but I think it should be more than sufficient for my needs.
The minor parts variations between the two circuits, besides those obviously directly caused by changing polarity, are to balance performance. It seems the only truly important parts are the two compensation capacitor values. Hopefully my old *** 20MHz DSO will be up to the task of finding real world values. Of the various transistor models I tried, it is ironic that the best performance seems to come from the ones I have most of in my parts bin.
Rising impedance at HF can be tamed with ~6.8uf of capacitance on the output, though you have to be careful with the ESR of the capacitor. Reduction in ripple rejection at HF can most easily be tamed by a small CLC filter before the regulator. A 1uf, 1uh 1ohm, 1uf pi filter knocks the heck out of the noise at HF, rolling it off past about 10KHz.
Remember that all of these values are simulator values, and my skill with simulation is sorely lacking, so take everything here with a shaker of salt.
