Atmel plays fast and loose with its new chip's low power credentials
On the face of it, this article gives the appearance that Atmel's raced into the lead by a substantial margin in the realm of low power ARM offerings - New ARM-powered chip aims for battery life measured in decades | Ars Technica
However a quick peek beneath the surface reveals all is not what it seems at first sight.
First a stand-out from the linked article :
Atmel, the San Jose-based microcontroller maker, today released samples of a new type of ultra-low power, ARM based microcontroller that could radically extend the battery life of small low-power intelligent devices. The new ... (MCUs) consume less than 35 microamps of power per megahertz of processing speed while active,
Radically eh? Less than 35 microamps /MHz is the claim here - wanna see how that stacks up?
Ostensibly the 35uA headline figure is a worthwhile improvement over NXP's latest offering - where NXP is claiming 55uA/MHz (the LPC5410x I posted about a while back). Intrigued, I looked deeper - into the new part's DS : https://www.atmel.com/Images/Atmel-42..._Datasheet.pdf Page 1109 has the relevant table for power consumptions vs supply current under different regimes (algorithms, clocking mode, regulator mode). Turns out that 35uA/MHz is a typical for the best case combination - all other cases are higher, some much higher. So 'under 35uA' is already looking decidedly shaky.
How Atmel have managed to game the numbers game is instructive. What they have which seems new is an on-chip buck regulator - a decent innovation in itself if you want an external supply higher than the CPU itself really needs. However this on-chip buck means that lower currents are being drawn when the supply voltage is higher (3.3V). The core normally operates on something below 2V - NXP's chip runs down to 1.62V for VCC suggesting a core voltage an LDO drop below that. This means that although the buck's taking 35uA, that's at 3.3V - the CPU will be taking more current - more than twice as much if the buck reg is very efficient and its putting out 1.5V. To see how its the buck reg and not the CPU process technology which is giving the apparent improvement, compare the uA/MHz figure when the LDO (linear) regulator's employed - the lowest current draw then is a none-too-impressive 75uA/MHz and that only up to 12MHz. Comparing the buck with LDO figures suggests to me that their CPU is running somewhere around 1.5V and drawing 75uA/MHz in its lowest power clocking mode.
Secondly the headline figure is only good for a particular clocking mode (L0 in the Atmel DS) which restricts the top freq to 12MHz. In the faster L2 mode it hits 48MHz but the power draw then isn't as impressive - roughly 30% worse.
Thirdly the DS states that there's one wait state involved when running from flash memory to hit the stated figures. NXP's figures are best when running from RAM (it has a generous amount for a uC) - there are no wait states then.
As one of the Ars commenters has already pointed out, the metric for comparing low power uCs should be in terms of useful operations per mW (DMIPs/mW) not in terms of current per MHz. uA/MHz is too easy to game.
When all these factors are taken into consideration, NXP still beats the Atmel offering comfortably in terms of usable CPU clout per mW. NXP also has more clout available as the top speed of their chip is 100MHz. And Atmel's offering is yet to be released whereas you can buy NXP's in their eval board today - with a 'free' Cortex M4 core thrown in for good measure
Update - here's an article which just from the first paragraph is painting a fairer picture because they say 'down to 35uA/MHz'. I'll look at how they're benchmarking it in depth myself : https://www.semiwiki.com/forum/conte...benchmark.html
A quick look reveals that the Atmel chip's real strengths aren't from the CPU itself but arise from its ultra-low power SRAM. It can keep that powered up and still sip less than 1uA - NXP's SRAM typically takes around 5X as much current. This means in any benchmark where the CPU is spending the vast majority of its time asleep but needs the SRAM contents preserved, Atmel is going to win. NXP though wins on ultimate lowest power - in its deep power down mode (at 1.62V) its sipping just 114nA to keep its RTC active. It can awaken from this state in just 200uS too, 10X faster than Atmel's CPU can from its lowest power state. So if you don't need permanent SRAM storage or have EEPROM or Flash for storage then NXP it seems will win.
I went over to EEMBC to see if there's enough information on ULPBench to estimate what NXP's score would be, but I can't find sufficient detail. The article on Semiwiki says '20,000 clock cycles of active work per second' but gives nothing away about what that active work consists of. Beginning with that though its possible to sketch out a scenario.
20k clock cycles when the CPU's running at 20MHz means a duty cycle of 0.1%. So a CPU running at 50uA/MHz takes 1mA active but this scales to 1uA by virtue of the duty cycle. Thus with SRAM retention, NXP is going to beat out Atmel when the duty cycle rises to 0.5% and above because in these scenarios the average current over 1s is dominated by the CPU, not the SRAM retention current. If you need a very low duty cycle then Atmel probably wins when SRAM retention is essential. Wake-up time though is not insignificant - if the CPU is drawing current when in its waking phase but can't do useful work this matters. A 0.1% duty cycle means an active time of 1mS each second - NXP waking from its lowest power mode adds 200uS to this, but Atmel adds 2mS. So perhaps NXP's position turns out better than at first sight.
Finally, of interest is the list of participants over at EEMBC :
Update2 - useful link to arcane aspects of ultra-low power design : www.ganssle.com/reports/ultra-low-power-design.html
Key take-aways - nobody's going to get 10years life out of a CR2032 feeding a practical circuit. Looks like NXP's optimization of CPU power is the smart choice as ultra-low SRAM leakage doesn't buy much given that the shelf life of the cell is 10years at max.
Update3 - TI has a new 'ultra-low power' CPU - the MSP432. This is based on a Cortex M4F running at 48MHz. They also look to play the numbers game on the uA/MHz because their headline figure is '90uA/MHz'. But on examining the DS (p19) I find that the lowest current consumption is with the DC/DC (read buck, just like Atmel) regulator in-circuit and that's 2.2mA @ 24MHz. Gives 91.7uA/MHz. The real current taken by the CPU is given in the LDO table which is 3.95mA @ 24MHz or 165uA/MHz. At top speed, 7.6mA which is 158uA/MHz. Once again nothing special. These figures are spec'd at 3V which suggests the CPU's running around 1.5V for a 90% efficient buck reg.
However a quick peek beneath the surface reveals all is not what it seems at first sight.
First a stand-out from the linked article :
Atmel, the San Jose-based microcontroller maker, today released samples of a new type of ultra-low power, ARM based microcontroller that could radically extend the battery life of small low-power intelligent devices. The new ... (MCUs) consume less than 35 microamps of power per megahertz of processing speed while active,
Radically eh? Less than 35 microamps /MHz is the claim here - wanna see how that stacks up?
Ostensibly the 35uA headline figure is a worthwhile improvement over NXP's latest offering - where NXP is claiming 55uA/MHz (the LPC5410x I posted about a while back). Intrigued, I looked deeper - into the new part's DS : https://www.atmel.com/Images/Atmel-42..._Datasheet.pdf Page 1109 has the relevant table for power consumptions vs supply current under different regimes (algorithms, clocking mode, regulator mode). Turns out that 35uA/MHz is a typical for the best case combination - all other cases are higher, some much higher. So 'under 35uA' is already looking decidedly shaky.
How Atmel have managed to game the numbers game is instructive. What they have which seems new is an on-chip buck regulator - a decent innovation in itself if you want an external supply higher than the CPU itself really needs. However this on-chip buck means that lower currents are being drawn when the supply voltage is higher (3.3V). The core normally operates on something below 2V - NXP's chip runs down to 1.62V for VCC suggesting a core voltage an LDO drop below that. This means that although the buck's taking 35uA, that's at 3.3V - the CPU will be taking more current - more than twice as much if the buck reg is very efficient and its putting out 1.5V. To see how its the buck reg and not the CPU process technology which is giving the apparent improvement, compare the uA/MHz figure when the LDO (linear) regulator's employed - the lowest current draw then is a none-too-impressive 75uA/MHz and that only up to 12MHz. Comparing the buck with LDO figures suggests to me that their CPU is running somewhere around 1.5V and drawing 75uA/MHz in its lowest power clocking mode.
Secondly the headline figure is only good for a particular clocking mode (L0 in the Atmel DS) which restricts the top freq to 12MHz. In the faster L2 mode it hits 48MHz but the power draw then isn't as impressive - roughly 30% worse.
Thirdly the DS states that there's one wait state involved when running from flash memory to hit the stated figures. NXP's figures are best when running from RAM (it has a generous amount for a uC) - there are no wait states then.
As one of the Ars commenters has already pointed out, the metric for comparing low power uCs should be in terms of useful operations per mW (DMIPs/mW) not in terms of current per MHz. uA/MHz is too easy to game.
When all these factors are taken into consideration, NXP still beats the Atmel offering comfortably in terms of usable CPU clout per mW. NXP also has more clout available as the top speed of their chip is 100MHz. And Atmel's offering is yet to be released whereas you can buy NXP's in their eval board today - with a 'free' Cortex M4 core thrown in for good measure
Update - here's an article which just from the first paragraph is painting a fairer picture because they say 'down to 35uA/MHz'. I'll look at how they're benchmarking it in depth myself : https://www.semiwiki.com/forum/conte...benchmark.html
A quick look reveals that the Atmel chip's real strengths aren't from the CPU itself but arise from its ultra-low power SRAM. It can keep that powered up and still sip less than 1uA - NXP's SRAM typically takes around 5X as much current. This means in any benchmark where the CPU is spending the vast majority of its time asleep but needs the SRAM contents preserved, Atmel is going to win. NXP though wins on ultimate lowest power - in its deep power down mode (at 1.62V) its sipping just 114nA to keep its RTC active. It can awaken from this state in just 200uS too, 10X faster than Atmel's CPU can from its lowest power state. So if you don't need permanent SRAM storage or have EEPROM or Flash for storage then NXP it seems will win.
I went over to EEMBC to see if there's enough information on ULPBench to estimate what NXP's score would be, but I can't find sufficient detail. The article on Semiwiki says '20,000 clock cycles of active work per second' but gives nothing away about what that active work consists of. Beginning with that though its possible to sketch out a scenario.
20k clock cycles when the CPU's running at 20MHz means a duty cycle of 0.1%. So a CPU running at 50uA/MHz takes 1mA active but this scales to 1uA by virtue of the duty cycle. Thus with SRAM retention, NXP is going to beat out Atmel when the duty cycle rises to 0.5% and above because in these scenarios the average current over 1s is dominated by the CPU, not the SRAM retention current. If you need a very low duty cycle then Atmel probably wins when SRAM retention is essential. Wake-up time though is not insignificant - if the CPU is drawing current when in its waking phase but can't do useful work this matters. A 0.1% duty cycle means an active time of 1mS each second - NXP waking from its lowest power mode adds 200uS to this, but Atmel adds 2mS. So perhaps NXP's position turns out better than at first sight.
Finally, of interest is the list of participants over at EEMBC :
- Analog Devices, ARM, Atmel, Cypress, Silicon Labs, Freescale, Microchip, Renesas, STMicro, TI.
Update2 - useful link to arcane aspects of ultra-low power design : www.ganssle.com/reports/ultra-low-power-design.html
Key take-aways - nobody's going to get 10years life out of a CR2032 feeding a practical circuit. Looks like NXP's optimization of CPU power is the smart choice as ultra-low SRAM leakage doesn't buy much given that the shelf life of the cell is 10years at max.
Update3 - TI has a new 'ultra-low power' CPU - the MSP432. This is based on a Cortex M4F running at 48MHz. They also look to play the numbers game on the uA/MHz because their headline figure is '90uA/MHz'. But on examining the DS (p19) I find that the lowest current consumption is with the DC/DC (read buck, just like Atmel) regulator in-circuit and that's 2.2mA @ 24MHz. Gives 91.7uA/MHz. The real current taken by the CPU is given in the LDO table which is 3.95mA @ 24MHz or 165uA/MHz. At top speed, 7.6mA which is 158uA/MHz. Once again nothing special. These figures are spec'd at 3V which suggests the CPU's running around 1.5V for a 90% efficient buck reg.
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