TNT,
The 'golden ear' comment was about hearing/not_hearing the hump.
My comment was about how clearly the datasheet explains putting the dac into synchronous mode. One setting turns off DPLL (jitter eliminator), another setting, 128_fs mode, allows the dac to run synchronously if DPLL is turned off. Also, synchronous mode works with MCLK at integer multiples of the 128_fs condition, even though they don't say so.
The 'golden ear' comment was about hearing/not_hearing the hump.
My comment was about how clearly the datasheet explains putting the dac into synchronous mode. One setting turns off DPLL (jitter eliminator), another setting, 128_fs mode, allows the dac to run synchronously if DPLL is turned off. Also, synchronous mode works with MCLK at integer multiples of the 128_fs condition, even though they don't say so.
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To put ESS dacs in synchronous mode, DPLL_Bandwidth must be set to 0. Otherwise, ASRC is still running.
Thank you for bringing the obvious to my attention.
Ok, this is the analog loop results; DAC output was attenuated using the ES9038PRO volume registers, to bring it in the ADC input range.
It happened I got slightly better result (see the attached screen shot), compared to the digital loop; but it is fair to assume both digital and analog loops are rendering about the same THD result -118dB or 0.00012%, and that without any extra filters like A-weighting, etc... Remember though, this is not at all digital and analog signal levels. Once again, runing the ADC and the DAC synchronously didn't make much of a difference in the measured results.
THD+N will be of course slightly worse, due to the ADC noise, I suppose around -113dB, not wasting time to redo all measurements for THD+N.
Everything would look fine, and I could go design the complete board and look into the analog part (attenuators, input protections, balanced/single ended conversion, auto scaling, etc..., which would be on a separate board) but... the ESS hump is there watching and killing the whole engineering fun. Not going anywhere until I'll sort out the hump, or decide to move to another DAC (I would not mind extra 2-3dB in THD at all levels, if it comes to that).
Just for the heck of it, I checked the results at the DAC input level matching the peak hump (see previous posts about); results are consistent, THD is -96dB, which is 22dB under the peak/optimum performance. This is a non starter for instrumentation
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My (another) conclusion: for digital audio reproduction, ES9038PRO is an amazing chip, the best one can get today, at least until AKM will resume the AK4499 and/or Rohm will finally start delivering the much praised BM94803 through the common distribution channels (not holding my breath for both, unfortunately). Since I have the ES9038PRO chips, I may eventually decide to design a DAC "for music" around them, and make the design available to the community, hopefully replacing those chines abominations, but that's not gonna happen anytime soon...
It happened I got slightly better result (see the attached screen shot), compared to the digital loop; but it is fair to assume both digital and analog loops are rendering about the same THD result -118dB or 0.00012%, and that without any extra filters like A-weighting, etc... Remember though, this is not at all digital and analog signal levels. Once again, runing the ADC and the DAC synchronously didn't make much of a difference in the measured results.
THD+N will be of course slightly worse, due to the ADC noise, I suppose around -113dB, not wasting time to redo all measurements for THD+N.
Everything would look fine, and I could go design the complete board and look into the analog part (attenuators, input protections, balanced/single ended conversion, auto scaling, etc..., which would be on a separate board) but... the ESS hump is there watching and killing the whole engineering fun. Not going anywhere until I'll sort out the hump, or decide to move to another DAC (I would not mind extra 2-3dB in THD at all levels, if it comes to that).
Just for the heck of it, I checked the results at the DAC input level matching the peak hump (see previous posts about); results are consistent, THD is -96dB, which is 22dB under the peak/optimum performance. This is a non starter for instrumentation
.My (another) conclusion: for digital audio reproduction, ES9038PRO is an amazing chip, the best one can get today, at least until AKM will resume the AK4499 and/or Rohm will finally start delivering the much praised BM94803 through the common distribution channels (not holding my breath for both, unfortunately). Since I have the ES9038PRO chips, I may eventually decide to design a DAC "for music" around them, and make the design available to the community, hopefully replacing those chines abominations, but that's not gonna happen anytime soon...
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I wonder if the hump is the reason Benchmark used the ES9028PRO instead of 9038. The performance is still excellent... maybe it's easier to get rid of.
I think my personal project will end up using PCM1792A if I get around to it before AKM comes back. It's not exciting but it's well documented and easily available.
+1 to Terry Demol for suggesting the possibility to get > 192 kHz by using an external filter at lower OSR and "abusing" the external filter mode feature. Maybe it won't perform very well, but I'm sort of curious to try it now.
I think my personal project will end up using PCM1792A if I get around to it before AKM comes back. It's not exciting but it's well documented and easily available.
+1 to Terry Demol for suggesting the possibility to get > 192 kHz by using an external filter at lower OSR and "abusing" the external filter mode feature. Maybe it won't perform very well, but I'm sort of curious to try it now.
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According to John Siau, they placed a higher priority on THD vs. SNR, and they got better results with the 9028 SMSL M500 Teardown & ESS ES9038Pro DAC Thermal Analysis | Page 7 | Audio Science Review (ASR) Forum
Yes, honestly I kept on putting this whole hump thing in the back of my mind after the AKM fire. I had planned on using it for measurements if solvable too, but maybe its just not doable and thankyou for throwing your hat into the ring in the search for characterising it syn08, although surely you could just use some silver cables to correct for the bass forward signature?
Given, currently it is not a known quantity, it cant be corrected for with any level of certainty, so as you say mate, its a nonstarter for high performance instrumentation. Damn it!! I was hoping the baseless rumours of it being gone on the 9038pro might turn out to be true.
Well, lets see if I can do some parallel testing on 9038q2m, but with a 'faster' opamp in the IV position ... lol. I figured i'd play with this and look into the IMD hump on the way to the full multi channel design and perhaps the dac availability landscape will change along the way. I'm using the superbly specced THS series. with open loop buf634 buffers (also doing a spin with the loop closed) DC is trimmed (input common mode voltage) at the input with resistors to VEE-, with output CM level shifted to match the BUF634 VCC/2 if required, using VCOM. Should make a very nice little balanced headphone amp as well.
Let the opamp 'rolling' begin!! on that note, you might notice its not exactly a DIY/mod friendly board and as a result, i'm afraid I wont be supplying PCBs and a build thread/support Ignore the digital (left) side, it's still in sketching phase and the power plane routing is not finalised. I will route a mux and clock, along with its regulator, but i'm doing a separate board with the clocks, logic and raspberry pi, with some isolation.
Anyway this is OT, just thought i'd chip in re IV stage 'speed' sending off for PCBs next week. it'll be a good test for my reflow oven jig. We'll see if I can get good results, or just hotplate and hotair.
the ugly grey chunks ar the XO and AVCC regs are common mode chokes. the STEP file ididnt come through properly into diptrace. regs are heavily filtered LTC6655 driven LT3042. clock reg is a fairly bog standard opa1611 buffered series reference (although I believe its defaulted to an LT1028 pattern, so its decomp pin is populated, that reminds me) and the output stage regs are LDO's from Ti. i'm interested to see how the THS perform compared to my old favorite, opa1632 FDA. They are well priced, so if they do well i'm going to buy a bunch, as datasheet specs are superb. There is also one of the ES9311 dual regs on the back (for VCAA_L/R). this will also be an interesting aspect of the process. I havent seen much talk of it, or its use on here.
Given, currently it is not a known quantity, it cant be corrected for with any level of certainty, so as you say mate, its a nonstarter for high performance instrumentation. Damn it!! I was hoping the baseless rumours of it being gone on the 9038pro might turn out to be true.
Well, lets see if I can do some parallel testing on 9038q2m, but with a 'faster' opamp in the IV position ... lol. I figured i'd play with this and look into the IMD hump on the way to the full multi channel design and perhaps the dac availability landscape will change along the way. I'm using the superbly specced THS series. with open loop buf634 buffers (also doing a spin with the loop closed) DC is trimmed (input common mode voltage) at the input with resistors to VEE-, with output CM level shifted to match the BUF634 VCC/2 if required, using VCOM. Should make a very nice little balanced headphone amp as well.
Let the opamp 'rolling' begin!! on that note, you might notice its not exactly a DIY/mod friendly board and as a result, i'm afraid I wont be supplying PCBs and a build thread/support
Ignore the digital (left) side, it's still in sketching phase and the power plane routing is not finalised. I will route a mux and clock, along with its regulator, but i'm doing a separate board with the clocks, logic and raspberry pi, with some isolation.Anyway this is OT, just thought i'd chip in re IV stage 'speed' sending off for PCBs next week. it'll be a good test for my reflow oven jig. We'll see if I can get good results, or just hotplate and hotair.
the ugly grey chunks ar the XO and AVCC regs are common mode chokes. the STEP file ididnt come through properly into diptrace. regs are heavily filtered LTC6655 driven LT3042. clock reg is a fairly bog standard opa1611 buffered series reference (although I believe its defaulted to an LT1028 pattern, so its decomp pin is populated, that reminds me) and the output stage regs are LDO's from Ti. i'm interested to see how the THS perform compared to my old favorite, opa1632 FDA. They are well priced, so if they do well i'm going to buy a bunch, as datasheet specs are superb. There is also one of the ES9311 dual regs on the back (for VCAA_L/R). this will also be an interesting aspect of the process. I havent seen much talk of it, or its use on here.
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While for the ES9038Q2M there's a clear solution to "eliminate" the hump in the IV stage, I've seen none for the ES9038PRO, in particular in mono mode (8 channels in parallel). The IV resistors are already 50ohm, lowering those doesn't seem to be a good idea, and anyway not sure if the same strategy would apply. Plenty of room for experimenting, but a solution is not obvious.
The cleanest ES9038PRO (2 x Mono mode) I've seen is the Gustard X26. Expensive product, but doesn't have a trace of IMD hump, and no trade off that I can tell.
Nobody cared to reverse engineer the IV stages, but based on some photos I've seen there's nothing outstanding there. Gustard had obviously support from ESS, I've heard rumors about the X26 using an external ASRC, the digital part of the X26 looks more complex than it should normally be, XMOS + CPLD + DSP chip + ARM CPU + plenty of memory, even with the Blue Tooth part implemented.
It would be very interesting to reverse engineer the X26, I may take that route if everything else will fail.
Nobody cared to reverse engineer the IV stages, but based on some photos I've seen there's nothing outstanding there. Gustard had obviously support from ESS, I've heard rumors about the X26 using an external ASRC, the digital part of the X26 looks more complex than it should normally be, XMOS + CPLD + DSP chip + ARM CPU + plenty of memory, even with the Blue Tooth part implemented.
It would be very interesting to reverse engineer the X26, I may take that route if everything else will fail.
One thing was that reported a ASR to fix the hump was to change the reference voltage at the I/V opamps non-inverting inputs to something less than AVCC/2. IIRC, the info was shared with permission of ESS. Don't know if anyone had any success with it. However, sometimes dacs have been seen with with a reference voltage of AVCC/3 or so (again IIRC, original 2-layer diyinhk ES9038PRO dac, and iancanada dual ES9038Q2M dac come to mind).
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Yes, I will be playing with input common mode voltage (its tunable on my board) and external digital filter, ASRC with local sync reclocking. I will expend some effort, because I do actually really like a well set up ESS dac, they are very capable parts, in spite of this annoyance. It is what it is; but it would be good to get to the bottom of it.