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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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Old 2nd April 2016, 12:10 AM   #4181
Blitz is offline Blitz  Germany
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Ian,

I have re-read all the manuals, but what I did not found was a hint for a clk select input, which I would need to integrate you Fifo or your clocks with the Beaglebone Black with Botic Drivers. Is there none or is it not needed ?

My amateur understanding:
-We want the best i2s quality. The BBB is capable of using external Masterclock as an input, your clock can out the masterclock, all good.
- Nevertheless, the BBB need to tell your clock which frequency he expects to get, therefore there is a clock select output from the BBB, which acko uses in his S03-board http://www.diyaudio.com/forums/attac...n-s03-bbb2.png, so we need a clk sel input somewhere in theory at your fifo or the clockboards, right ?

As I own three of your fifos and four of you clockboatds, I would like to use them to integrate them with the BBB and not use the internal clocking of the BBB as that is set only right for 48khz and is anyhow not at the same quality, plus it has been reported using the same clocks brings audible advantages...
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Old 4th April 2016, 02:22 PM   #4182
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by Blitz View Post
Ian,

I have re-read all the manuals, but what I did not found was a hint for a clk select input, which I would need to integrate you Fifo or your clocks with the Beaglebone Black with Botic Drivers. Is there none or is it not needed ?

My amateur understanding:
-We want the best i2s quality. The BBB is capable of using external Masterclock as an input, your clock can out the masterclock, all good.
- Nevertheless, the BBB need to tell your clock which frequency he expects to get, therefore there is a clock select output from the BBB, which acko uses in his S03-board http://www.diyaudio.com/forums/attac...n-s03-bbb2.png, so we need a clk sel input somewhere in theory at your fifo or the clockboards, right ?

As I own three of your fifos and four of you clockboatds, I would like to use them to integrate them with the BBB and not use the internal clocking of the BBB as that is set only right for 48khz and is anyhow not at the same quality, plus it has been reported using the same clocks brings audible advantages...
Hi Blitz,

I have a BBB. Can you please let me know which software do you use for this slave mode playing back?

Dual XO II might be possible for this job, but I have to do some test to figure out how to pass the control signal.

Regards,
Ian
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Old 4th April 2016, 02:32 PM   #4183
Eldam is offline Eldam  France
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Is there any risk of digital ground loop because the MCL link would be above the Isolator (gnd direct between the BBB and clock board, so no isolation anymore ?)

Could be fun if so to look at if the good Odroid C1+ (because it's above 192 K Hz layout behavior) can be slavered as well
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Old 4th April 2016, 11:55 PM   #4184
Blitz is offline Blitz  Germany
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Ian, that would be great...

I am talking about the Botic Driver which has been originally designed for Hermes/Chronus....an isolator/clock/reclocker from twistedp.

http://bbb.ieero.com

The software enables the audio-portion of the bbb...and is universal.
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Old 5th April 2016, 04:11 PM   #4185
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by analog_sa View Post
Hi Ian

Are you saying that bit errors are not just old wives tales then?

As the FIFO is the last down the chain of software player/ OS/ spdif/ usb / Rpi/etc, may i suggest a feature for the next edition?

An algo checking the entire chain is bit perfect. Say you short a jumper and the processor gets into testing mode. A test file, or files for various sampling rates and dsd is played at the source and the FIFO lights an LED indicating a correct checksum. Shouldn't be hard to implement.

What do you think? One less worry in a poor audiophile's life
Quote:
Originally Posted by analog_sa View Post
If one is happy with checking just pcm up to 192kHz, a small board with a tranceiver chip should suffice. Convert the i2s from the fifo output to spdif, loop it back into a PC and voila, you can do bit comparisons. But it is work
Hi analog_sa,

That's a very good idea.

Actually I did this to every FIFO KIT on my test fixtures when I was doing finial test before shipment.

I designed two FPGA based test fixtures with built in I2S testing pattern generator,I2S receiver and error detector.

One is 32bit for FIFO KIT I2S loop test, the other is 24bit for FIFO KIT S/PDIF loop test (has S/PDIF board in system). If any bit was wrong during test, error indication LEDs with be lit.

To extent this testing chain to with audio file - player - driver .. included, we need a testing patter .way file. With it we can do bit perfect test to whole system rather than FIFO only.

I can do this test right now if we can record my testing pattern digitally into a .wav file. Either in 32bit from I2S or in 24bit from S/PDIF

I'll take it into consideration to see if I can include this bit perfect testing feature into my new multi-channel I2S/DSD FIFO project.

An alternative way to achieve this kind of bit perfect test is to play a dts file, if the DTS light on the receiver which is placed at the end of the digital audio chain is lit, bit perfect will be confirmed.

Thanks again for your good idea.

Regards,
Ian
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Old 5th April 2016, 04:31 PM   #4186
Julf is offline Julf  Europe
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Originally Posted by iancanada View Post
I'll take it into consideration to see if I can include this bit perfect testing feature into my new multi-channel I2S/DSD FIFO project.
I think it would be a great feature, just to ease concerns people might have.

Just out of curiosity, did you come across many conditions causing actual bit errors in your tests?
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Old 5th April 2016, 04:59 PM   #4187
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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Originally Posted by Julf View Post
I think it would be a great feature, just to ease concerns people might have.

Just out of curiosity, did you come across many conditions causing actual bit errors in your tests?
Hi Julf,

My test was @ 32bit 384KHz for 2 minutes. 98% can pass the test. 2% failure caused by SMT assembly issues such as short or disconnection in production. Nothing unstable in between. All of those that pass 2 minutes test will pass 2 hours test without problem. That's the power or digital audio hardware.

According to my experience, most of non-bit-perfect issues were caused by software, such as compressing, DSP enhance/effect/filtering, up-sampling and digital volume control. I this case, to do bi-perfect verification from very beginning of the audio stream chain would be very important.

Ian

Last edited by iancanada; 5th April 2016 at 05:07 PM.
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Old 5th April 2016, 05:26 PM   #4188
Julf is offline Julf  Europe
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Quote:
Originally Posted by iancanada View Post
My test was @ 32bit 384KHz for 2 minutes. 98% can pass the test. 2% failure caused by SMT assembly issues such as short or disconnection in production. Nothing unstable in between. All of those that pass 2 minutes test will pass 2 hours test without problem. That's the power or digital audio hardware.
That was pretty much my expectation

Quote:
According to my experience, most of non-bit-perfect issues were caused by software, such as compressing, DSP enhance/effect/filtering, up-sampling and digital volume control. I this case, to do bi-perfect verification from very beginning of the audio stream chain would be very important.
I agree. I always keep wondering about how many audiophiles who obsess about cables and power supplies might actually have a non-bit-perfect software chain without realizing it.

Of course, some things like digital volume control and up/resampling are "mostly harmless" but definitely not bit perfect - by definition.
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Old 7th April 2016, 02:27 PM   #4189
Crom is offline Crom  United Kingdom
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Default New board feature request

Hi Ian,

A further feature request for the new board, if I may:

I am looking to use the board with dual mono Twisted Pear Bufallo IIISE. Part of the drive to use your new board is to enable DSD playback. However, I've discovered a limitation with the DAC board (specifically, the internal channel mapping within the ESS DAC chip) that means that by default a dual mono BIIISE will play back in mono! The problem is identified in this post:

DSD problem on Doble Mono configuration

and a solution is discussed from here in the same thread:

DSD problem on Doble Mono configuration- Page 2

The current solution uses a switch here:

OTTO-II 2:1 Switching Module

However, this solution introduces signal propagation delay and I was wondering whether a more elegant solution would be possible to integrate into your new FIFO project to allow DSD/PCM playback without adding further elements into the signal chain?

All the best,
Crom
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Old 7th April 2016, 02:58 PM   #4190
BrianDonegan is offline BrianDonegan  United States
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by Crom View Post
The current solution uses a switch here:

OTTO-II 2:1 Switching Module

However, this solution introduces signal propagation delay and I was wondering whether a more elegant solution would be possible to integrate into your new FIFO project to allow DSD/PCM playback without adding further elements into the signal chain?
Just a note... the propagation delay through the OTTO-II is <.25ns (>4GHz), and should equal across the four channels. I don't think this is something you need to worry about.
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