this is a link to an early version of the app note in the data book that i referred to earlier:
https://storycase.co.uk/radio/wp-content/uploads/2017/05/HitachiMosFets.pdf
and here's a link to the old Hitachi Power MOSFET databook from 1985 (some of you younger guys never had a paper version): https://ia601906.us.archive.org/11/...6/1985_D11_Hitachi_Power_MOSFET_Data_Book.pdf (just so you know, it's a 22MB file)
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The LTP needs some kind of supply noise filtering (R+C), otherwise you have feedback from the supply rail. Be sure to wire the output transistors directly to the power supply caps and not share a wire with the rest of the amp. And you need a VAS current that does not vary with the supply voltage, ie an LTP CCS (not just a resistor) or the VAS with transistors monitoring the emitter resistor (total VAS current), or both.
For a +/-45V supply you need a slew rate of 45V*20KHz*2pi= 5.6V/uS x margin ~=10V/uS so the VAS w/o drivers needs to be about ~2nF*10V/uS = 20mA. And 45V*20mA=900mW, ie a bit much for 2N5551 and 2N5401. Maybe 10mA would be OK with a lower voltage supply. Being a P-P VAS doubles the peak VAS current, so 10mA may be good enough.
I would leave a place for degen resistors in the IPS so that you can reduce the loop gain if it oscillates.
C4 is probably a bad idea because it cripples the compensation for TR3.
A "speed-up"cap across the bias resistor (RFV1) is a good idea.
An RC (~22p+~1K) across the feedback resistor R7 improves feedback stability, but I would not just use a cap because that makes for RF rectification in the IPS.
A Zobel network R15+C7 is not useful on a follower output but the inductor L1 is needed and needs a damper resistor across it.
Nuff 4 now.
For a +/-45V supply you need a slew rate of 45V*20KHz*2pi= 5.6V/uS x margin ~=10V/uS so the VAS w/o drivers needs to be about ~2nF*10V/uS = 20mA. And 45V*20mA=900mW, ie a bit much for 2N5551 and 2N5401. Maybe 10mA would be OK with a lower voltage supply. Being a P-P VAS doubles the peak VAS current, so 10mA may be good enough.
I would leave a place for degen resistors in the IPS so that you can reduce the loop gain if it oscillates.
C4 is probably a bad idea because it cripples the compensation for TR3.
A "speed-up"cap across the bias resistor (RFV1) is a good idea.
An RC (~22p+~1K) across the feedback resistor R7 improves feedback stability, but I would not just use a cap because that makes for RF rectification in the IPS.
A Zobel network R15+C7 is not useful on a follower output but the inductor L1 is needed and needs a damper resistor across it.
Nuff 4 now.
I agree that the tail current in the input stage should be constant current, but I think that if the input stage is made constant current, it is sufficient to leave the VAS as a resistor.
It is better not to make the circuit too complicated.
I think ~2nF is the input capacitance of the output stage, but in the case of a source follower, the gate-source capacitance is approximately 1/(1+gm*RL)
decreases to Even if gm=1S, RL=4Ω, it will be about 1/5.
C4 is required. #39 is already explained.
I think Zobel is also effective.
In particular, these lateral MOSs are case-sourced and, when tightly attached to a heatsink, will have a capacitive load of several 100 pF.
I agree with everything else. In particular, I strongly recommend adding degeneration resistors to the input stage and adding R+C in parallel to the feedback resistor.
Wish I knew that before, would have saved a lot of time.
Yes, needs some tweaking but at least it may work. How did you determine the unity loop gain?
Thanks, interesting. Needs to be studied more closely in the future. Though, I noted one interesting thing. It says that to little current supply from the VAS will increase distortion at high frequencies with MOSFET output stages, since the current need varies with frequency. The circuit in the article uses 5 mA for VAS and 1 mA for the input stage. Sounds like I should try to increase the VAS current at least then.
The unity loop gain frequency is
f(ULG)=gm*β/(4π*Cc)
gm is the gm of the input stage Tr, and if the collector current is Ic,
gm≒39Ic
It can be calculated with
For example, if Ic=0.5mA
19.5mS
Ic is the current per piece. That is half of the tail current.
β is negative feedback rate
For the circuit diagram above
β＝R6/(R7+R6)
Cc is the compensation capacitance.
In the case of 2-pole phase compensation, it is two capacitors in series.
For example 22p and 560p, use a series capacitance value of 21.17pF.
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part of the fun in engineering is making all the judgement calls.
choosing the VAS devices and currents is a case in point. in these designs, the VAS does the high voltage swing (the OPS is a voltage follower and just provides current gain). you also want fast transistors (i.e. low capacitance) in a VAS. but semiconductor physics dictates that "fast" transistors are not usually rated "high" voltage. so, you choose a transistor from the special video driver device category for the voltage range and low capacitance. Low capacitance also comes from using relatively smaller dies, so your device might not have the SOA and current handling you want to swing high voltage AND push "high" current into the mosfet gates for good slew rate and lower high frequency distortion (even though the mosfet input capacitance is bootstrapped in a source follower configuration). And with the higher voltage rating, it might not have the highest/best hFE linearity, etc. what to do, what to do....?
as has already been hinted at, for a number of reasons, the 2N5551 and 2N5401 are likely not the best parts to use in this VAS. you might consider some compound transistor arrangements (cascode, darlington, etc.) to try to work around some of these issues. but then, you start wondering about circuit complexity and impacts to stability (you've got to be careful with cascodes possibly contributing to oscillations).
this basic design has been reworked a number of times at this site already. in addition to reading the comments from steveu above and articles that i pointed out, it may also be worth the while to look at the designs and rationale developed during these other investigations to save you from going down a rabbit hole and finding a skunk.
but, i understand it is fun just playing around also.
good luck !
choosing the VAS devices and currents is a case in point. in these designs, the VAS does the high voltage swing (the OPS is a voltage follower and just provides current gain). you also want fast transistors (i.e. low capacitance) in a VAS. but semiconductor physics dictates that "fast" transistors are not usually rated "high" voltage. so, you choose a transistor from the special video driver device category for the voltage range and low capacitance. Low capacitance also comes from using relatively smaller dies, so your device might not have the SOA and current handling you want to swing high voltage AND push "high" current into the mosfet gates for good slew rate and lower high frequency distortion (even though the mosfet input capacitance is bootstrapped in a source follower configuration). And with the higher voltage rating, it might not have the highest/best hFE linearity, etc. what to do, what to do....?
as has already been hinted at, for a number of reasons, the 2N5551 and 2N5401 are likely not the best parts to use in this VAS. you might consider some compound transistor arrangements (cascode, darlington, etc.) to try to work around some of these issues. but then, you start wondering about circuit complexity and impacts to stability (you've got to be careful with cascodes possibly contributing to oscillations).
this basic design has been reworked a number of times at this site already. in addition to reading the comments from steveu above and articles that i pointed out, it may also be worth the while to look at the designs and rationale developed during these other investigations to save you from going down a rabbit hole and finding a skunk.
but, i understand it is fun just playing around also.
good luck !
here's just one somewhat recent example of the many variants around here:
https://www.diyaudio.com/community/threads/visiting-an-old-friend.403610/#post-7462031
notice the specs of the devices chosen for the VAS compared to the 2N5551/2N5401.
https://www.diyaudio.com/community/threads/visiting-an-old-friend.403610/#post-7462031
notice the specs of the devices chosen for the VAS compared to the 2N5551/2N5401.
Sorry.
The formula for unity loop gain frequency in #86 was incorrect.
Correctly,
f(ULG)=gm*β/(2π*Cc)
As a side note,
The value of Cc includes the Cob of the transistor.
gm≒39Ic's 39 is
means 1/Vt.
Vt is thermal voltage Approximately 26mV at room temperature
This gm is constant regardless of the type of BJT.
In the case of FET, it differs depending on the type.
If there is a degenerate resistance Re in the emitter like 330Ω in the figure below
use the value of
gm≒39Ic/(1+39Ic*Re)
Having Re like this is convenient because you can adjust gm (that is, adjust the loop gain) with the value of Re.
The formula for unity loop gain frequency in #86 was incorrect.
Correctly,
f(ULG)=gm*β/(2π*Cc)
As a side note,
The value of Cc includes the Cob of the transistor.
gm≒39Ic's 39 is
means 1/Vt.
Vt is thermal voltage Approximately 26mV at room temperature
This gm is constant regardless of the type of BJT.
In the case of FET, it differs depending on the type.
If there is a degenerate resistance Re in the emitter like 330Ω in the figure below
use the value of
gm≒39Ic/(1+39Ic*Re)
Having Re like this is convenient because you can adjust gm (that is, adjust the loop gain) with the value of Re.
Ok, I see. That formula tells me that the capacitance of the smallest capacitor in the two pole network greatly affects the loop gain (due to the series capacitance). I agree that 27p seems very small in general, but it seems like that was this circuit needs (tried a lot different values now). Higher values kills the slew rate, so that's a trade off.
Degeneration could also work, tried with 100 ohm. Bigger values also kills the slew rate, but of cause its a very useful trick if an amp becomes unstable.
Looking back to the original Hitachi circuit I now realize that the conversion from +/-45V to +/-25 lowered the VAS current too much. The original circuit uses 5 mA, which shouldn't be lower according to the article. Don't know why I missed this, got the it right with the CCS version.
However I found it very tricky to get the DC balance right then tweaking the resistors values, so I replaced the R9 + C4 with a transistor instead, thanks @mason_f8 ! And it seems to work in simulation so far. Figures are quite impressive; 0,0002 THD % 1 khz at 1W and rising to only 0,015 % 20kHz at 25W.
Not really sure how much the two pole compensating network actually affect the circuit. Removing it only slightly increases distortion from 0,015 to 0,03 % or so at 20kHz. The biggest difference is the VAS current I think. Will probably have to build it this weekend and find out...
Degeneration could also work, tried with 100 ohm. Bigger values also kills the slew rate, but of cause its a very useful trick if an amp becomes unstable.
Looking back to the original Hitachi circuit I now realize that the conversion from +/-45V to +/-25 lowered the VAS current too much. The original circuit uses 5 mA, which shouldn't be lower according to the article. Don't know why I missed this, got the it right with the CCS version.
However I found it very tricky to get the DC balance right then tweaking the resistors values, so I replaced the R9 + C4 with a transistor instead, thanks @mason_f8 ! And it seems to work in simulation so far. Figures are quite impressive; 0,0002 THD % 1 khz at 1W and rising to only 0,015 % 20kHz at 25W.
Not really sure how much the two pole compensating network actually affect the circuit. Removing it only slightly increases distortion from 0,015 to 0,03 % or so at 20kHz. The biggest difference is the VAS current I think. Will probably have to build it this weekend and find out...
The 2SC3505 vs 2N5551? 300/160 V, 300mA/600mA, 150 Mhz/100-300Mhz.
I admit that the reason I picked 2N5551 and 2N5504 is that I have a lot of them, but are they really that bad choice for the VAS and for what reason?
Maximum heat dissipation from 2SC3505 are of cause higher but don't think it will be a problem. Running the VAS at 5mA and lets assume 50V (absolute max) across the transistors, that's 0,005*50=250mW. And maximum power for 2N5551 is 600mW. TR6 gets a little hot actually, feels a little warm to touch, but no problem.
Built a working amplifier yesterday and the specs are quite good now. Close to the distortion levels stated in the Hitachi original article. Use the design from previous post #90, but had to do some changes, see attached schematic.
R1 does seem to affect the distortion of the circuit a lot. I have no idea why, thought it only made a RC low pass filter for RF frequencies. However it does, and the original circuit used 2k2 so I picked it too.
The resistor of the two pole compensating network (R7 and R13) now connects to negative supply instead of ground. I think this is a better idea, but I can’t really explain why.
With a quiescent current of 98mA I was able to measure following;
THD @ 1 khz;
0.0033% 1 W 8 ohm
0.0051% 20W 8 ohm
0.0066% 1W 4 ohm
0.016% 25W 4 ohm
Slew rate approx 45Vµ/S (8 ohm, 20khZ square wave, approx 37V for 4 ohm)
DC offset -3mV
The square wave response shows some ringing, so stability may be a problem. But I guess slowing down the amp by degeneration and/or bigger compensating cap will take care of this. 45V slew rate is much more than needed for 20W amp anyway.
It is still unknown that the actual distortion at higher frequencies will be, but so far this looks like an decent amp to me. Interesting was that I tried with a single compensating capacitor of 27p first, which worked ok. But changing to the two pole compensating network lowered the distortion significantly, dropped about 50% at all power settings. Also slew rate improved from 27 to 45 V/µS. I have no idea why…
R1 does seem to affect the distortion of the circuit a lot. I have no idea why, thought it only made a RC low pass filter for RF frequencies. However it does, and the original circuit used 2k2 so I picked it too.
The resistor of the two pole compensating network (R7 and R13) now connects to negative supply instead of ground. I think this is a better idea, but I can’t really explain why.
With a quiescent current of 98mA I was able to measure following;
THD @ 1 khz;
0.0033% 1 W 8 ohm
0.0051% 20W 8 ohm
0.0066% 1W 4 ohm
0.016% 25W 4 ohm
Slew rate approx 45Vµ/S (8 ohm, 20khZ square wave, approx 37V for 4 ohm)
DC offset -3mV
The square wave response shows some ringing, so stability may be a problem. But I guess slowing down the amp by degeneration and/or bigger compensating cap will take care of this. 45V slew rate is much more than needed for 20W amp anyway.
It is still unknown that the actual distortion at higher frequencies will be, but so far this looks like an decent amp to me. Interesting was that I tried with a single compensating capacitor of 27p first, which worked ok. But changing to the two pole compensating network lowered the distortion significantly, dropped about 50% at all power settings. Also slew rate improved from 27 to 45 V/µS. I have no idea why…
As others have mentioned, this may be due to the selection of transistors in the input stage. A small signal with a large hfe and a small cob is suitable here.
Input capacitance also has a large effect on feedback stability. The capacitance on the inverting input side forms an extra pole with the impedance of the feedback circuit (R6//R7).
Yes, it doesn't matter whether it's ground or the power rail, since both are ground in AC terms. However, there will be a difference in PSRR, so when the final constants have been decided, we recommend running a simulation to put a signal voltage source on the positive and negative power supplies and perform AC analysis of the output to determine which one to use.
Observing square waves has two purposes.
One is observation at large amplitudes, with the purpose of measuring slew rate and investigating whether recovery from saturation is appropriate.
Another objective is to check the stability of the feedback within linear operation using small signals. Many op-amps datasheets also list both.
The latter should not use a large signal that would conflict with the slew rate. Slew rate is a nonlinear operation that occurs when the current in a part of the circuit saturates.
Also, since the input filter is outside the feedback loop, it interferes with observation. However, it is a hassle to remove.
In that case, we recommend the current injection method.
Add a square wave to the inverting input (base of Tr2) via a resistor.
Use a value for this resistor that is sufficiently larger than R6 (20 times or more) so as not to change the feedback factor.
Place this resistor on the amplifier side. Do not place it on the oscillator side and extend the cable because the capacitance of the inverting input increases.
I think the output should be around 1Vpp. If you check at a higher frequency, you can better see the overshoot and ringing at the rise and fall. At this level, it should be safe even above 100kHz.
The output L is also outside the feedback loop, so the observation point will be in front of L.1
Although it is outside the feedback loop, it does affect the loop characteristics.
Input filters also affect loop characteristics. my previous post
In addition, in the case of 2-pole phase compensation, even if the compensation is appropriate, a peak will occur in the high frequency range (near the unity loop gain), and overshoot will usually occur in the square wave response. This can be corrected by adding an R+C circuit in parallel to the feedback resistor (R7).
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I didn't knew that. But makes sense now, thanks.
And the purpose of this method is to eliminate the influence of the input filter, am I correct? I'll have to try this...
Anyway, think I got rid of the ringing. It appears that the most effective way was not too increase the compensating caps (but increased it to 47p anyway) nor adding degeneration. Instead putting a RC link across the feedback resistor (as previously suggested) did the trick. Values were very picky though, settled at 22p + 4k7 ohm, first by simulation and then by testing. Slew rate dropped to about 15 V/µS, but then I think this is acceptable for a 25W amp into 8ohm. Distortion wasn't affected at all for 1khz (actually improved a bit, but my measurements ain't that really accurate). So wish to be able to measure the higher frequency distortion now...
Yes, inputting a square wave through the input LFP slows down the rise and fall, so it is possible to overlook instability at high frequencies.
It was good.
The figure below is an example of the open loop characteristics of another circuit.The dotted line is 1-pole compensation, and the solid line is 2-pole compensation and green is gain, red is phase shift.
It can be seen that the gain of the 2-pole compensation increases in the audio band.
For an amplifier with a gain of about 30dB, the unity loop gain will be about 2MHz. The phase margin is approximately 65°.
By the way, I forgot to mention,
The pier R of the compensation circuit is determined by the frequency at which the gain changes from -40dB/dec to -20dB/dec and is calculated using the following formula.
f (change point) = 1/(2π(Cc1+Cc2)*Rpier)
In the example above, it is 241kHz.
The pier R is not visible in your circuit diagram, but for example, if it is 2.2kΩ,
1/(2π*(517p*2.2k))=140kHz
It becomes.
Increasing this frequency increases loop gain and lowers distortion, but reduces phase margin.
A value of about 1/5 to 1/10 of the unity loop gain frequency is recommended.
However, changing this value also changes the optimal value of the correction R+C in parallel with the feedback resistor.
Interesting. I did just as you suggested, used a 22k resistor to feed a square wave signal directly to base of Q2. looking at the signal with a scope before the output inductor showed no signs of ringing at all. Actually I thought what I had slowed down the amp a bit to much. Slew rate was quite low, (about 15V/µS rising and 12 V/µS falling). But then this wasn't the purpose of this test, right? Measuring the output at full power into a 8 ohm load, show a slew rate of about 30V/µS instead, which is good I think.
Here's how the "internal" square wave of 20kHz looks like;
It's 1k, in the attached pdf is the whole schematic, sorry wasn't really clear in previous post.
Picked 1k just because it's a textbook example standard value. And I wasn't aware of that formula actually, but I noted that it had some affect to the simulations but did not know how for sure. So thanks for that information.
Inserting 1k into the formula gives; f=307 khz, and unity unity loop gain frequency that i got from LTspice simulation was about 8Mhz (don't know why I couldn't get it right using your formula). That means about 1/26, so what does that tells us?
Anyway I think the amp seems to preform well now, stability or speed does not seem to be a problem. So to test the distortion at higher frequencies, I very quickly build a 10khz sine wave generator which tested <0,001% second harmonic distortion. Used it to measure the distortion, and it tested about 0,0033 % into 8 ohm and 0,009 % into 4 ohm at 1 W. Using a soundcard and REW to te measure the distropn I'm not abale to measeure the thigher harmonics (or maybe but I haven't figuered it out yet). But then measureing distrotion a 1 kHz I've seen that the second order harmonics is about 99% of the THD, so I'm guessing this is the case now too. If so this is looking quite promissing.
Yes, this test does not measure the correct slew rate. Measured in large signal operation.
Typically, for this configuration, the slew rate is
calculated as
(IPS tail current)/(compensation capacitance).
Tail current=1.1mA, Cc=42.73pF
Then
SR=25.7V/μsec
is calculated.
This value is for 1-pole compensation, so it may be a little higher for 2-pole.
I tried calculating the ULGF based on your attached PDF schematic.
The current flowing through Tr1 (or Tr2) of IPS is 0.55mA, so gm=21.45mS.
Series value of compensation capacitance Cc=42.73pF.
β=330/(330+12000)=0.02676.
As f(ulg)=2.14MHz is calculated.
I think this frequency is a reasonable and appropriate value for a power amplifier.
The frequency of 307kHz that returns to -20dB/dec for 2-pole compensation is within the range of 1/5 to 1/10 of f(ulg), which I think is appropriate.
I don't know why f(ulg)=8MHz in your LTspice simulation. The square wave response waveform inside the loop looks very clean and stable.
By the way
Looking at the evolution of circuit diagrams so far, you have changed the gain (1/β) many times.
I believe that the gain is a specification that should be determined first, and is not a specification that is determined based on circuit design considerations. If you are doing DIY for your own use, you should decide on a value that is easy for you to use. If the amplifier you've been using so far is easy to use, you can choose the same value, or if you're not satisfied, you can change it.
As formula #86 shows, if the gain changes, the appropriate phase compensation value will also change.
We recommend fixing the gain first and then determining the phase compensation value.
The current gain of your circuit is 31.57＝30dB (1/β is 37.36, but it is attenuated to 0.845 by R1 and R2)
Is this okay?
That is close to what I measured.
Well that sounds better. I'm quite novice at LTspice so probably did something wrong. Also according to my LTspice simulations the amp would fulfill the Nyquist stability criterion with the values I choosed, but the amp appears to be stable to during the test so I thought it was wrong.
Yes the current gain is ok. I was aiming for a inupt sensitivity of approx 1V pp for full output during my design. I know that it has changed a lot of times, well noted and thank you for putting up with my inconsistency. For some reason the simulations genrated higher gain than the real prototype, so I changed the gain of the real amplifer by reducing the ground feedback resistor R6. Also i changed the input impedance a few times, stucking at 12k because I ran out of 10k resistors. R1 was tricky to change for some reason, so i left it as the original 2k2. Thought it was only a lowpass filter together with C4, wich was 47p origanlly. 2k2 + 47pF equals -3db of 1,5Mhz, and I I used 2k2 +100pf equals 0,7Mhz, but since it works ok I think I'll just leave it as so.
However I did not thought about how it affected the appropiate phase compensations during this process. But it makes makes sense that you wrote and I'll have in mind then I'm designing my next projects.
So I had to try with a CCS for the input stage still. This time I substituted R4 with an approx 1mA CCS, see both attached schematics for reference. I picked 1 mA (or close 0,98 with the current values) because that’s what used to drive the input stage in the original article from Hitachi. Soldered the components of the CCS together pin to pin, and substituted R4 with them. Measured the distortion of the same board everything, but with resistor R4 instead of CCS. That way the results should be as comparable as possible I thought. The results were as follows;
with resistor R4;
0.0023 % THD 1khz 1W 8 ohm 0.0047 % 1khz THD 1W 4 ohm
0.0045 % THD 1khz 20W 8 ohm 0.0013 % 1khz THD 20W 4 ohm
0.0060 % (2nd order) 10khz 1W 8 ohm 0.013 % 10khz (2nd order) 1W 4 ohm
0.0070 % (2nd order) 10khz 25W 8 ohm 0.015 % 10khz (2nd order) 20W 4 ohm
with CCS;
0.0017 % THD 1khz 1W 8 ohm 0.0021 % 1khz THD 1W 4 ohm
0.0021 % THD 1khz 20W 8 ohm 0.0054 % 1khz THD 25W 4 ohm
0.0057 % (2nd order) 10khz 1W 8 ohm 0.013 % 10khz (2nd order) 1W 4 ohm
0.0040 % (2nd order) 10khz 25W 8 ohm 0.0088 % 10khz (2nd order) 25W 4 ohm
With the CCS were is a noticeable drop in distortion, mostly at 4 ohm. Also interesting that distortion a 10khz drops at higher power with the CCS. In my opinion the circuit can benefit from a CCS based on these numbers. Probably worth the 2 extra transistors…
Why it’s behaving like this I cannot really say, but my theory is that the current through the input stage affect the current trough the VAS. If this current is kept stable the distortion may be lower. Since there's is no regulation with a single resistor, the current isn’t kept stable with the small deviation of supply voltages caused by the amp. At 4 ohm load the amp draws more current, thus the bigger ripple voltage from a unregulated PSU and without the CCS the input current will vary more.
I used my lab bench regulated PSU during the test, it’s pretty well regulated but of cause not free from ripple. However, a common unregulated power amp PSU will most likely vary more in voltage. Also noted the I (accidentally) change the VAS current from 4.95mA with the resistor to 4.62mA with the CCS due to slightly lower current through the input stage. The VAS current is a important variable for this circuit as mentioned in the Hitachi article.
with resistor R4;
0.0023 % THD 1khz 1W 8 ohm 0.0047 % 1khz THD 1W 4 ohm
0.0045 % THD 1khz 20W 8 ohm 0.0013 % 1khz THD 20W 4 ohm
0.0060 % (2nd order) 10khz 1W 8 ohm 0.013 % 10khz (2nd order) 1W 4 ohm
0.0070 % (2nd order) 10khz 25W 8 ohm 0.015 % 10khz (2nd order) 20W 4 ohm
with CCS;
0.0017 % THD 1khz 1W 8 ohm 0.0021 % 1khz THD 1W 4 ohm
0.0021 % THD 1khz 20W 8 ohm 0.0054 % 1khz THD 25W 4 ohm
0.0057 % (2nd order) 10khz 1W 8 ohm 0.013 % 10khz (2nd order) 1W 4 ohm
0.0040 % (2nd order) 10khz 25W 8 ohm 0.0088 % 10khz (2nd order) 25W 4 ohm
With the CCS were is a noticeable drop in distortion, mostly at 4 ohm. Also interesting that distortion a 10khz drops at higher power with the CCS. In my opinion the circuit can benefit from a CCS based on these numbers. Probably worth the 2 extra transistors…
Why it’s behaving like this I cannot really say, but my theory is that the current through the input stage affect the current trough the VAS. If this current is kept stable the distortion may be lower. Since there's is no regulation with a single resistor, the current isn’t kept stable with the small deviation of supply voltages caused by the amp. At 4 ohm load the amp draws more current, thus the bigger ripple voltage from a unregulated PSU and without the CCS the input current will vary more.
I used my lab bench regulated PSU during the test, it’s pretty well regulated but of cause not free from ripple. However, a common unregulated power amp PSU will most likely vary more in voltage. Also noted the I (accidentally) change the VAS current from 4.95mA with the resistor to 4.62mA with the CCS due to slightly lower current through the input stage. The VAS current is a important variable for this circuit as mentioned in the Hitachi article.