^ Not exactly.
Valve dac FPGA does upsampling but not exactly ASRC, and certainly not conversion of PCM to DSD. In fact, some of the guys building those dacs are interested in the AK4137 boards of this thread so they can convert PCM to DSD256.
Valve dac FPGA does upsampling but not exactly ASRC, and certainly not conversion of PCM to DSD. In fact, some of the guys building those dacs are interested in the AK4137 boards of this thread so they can convert PCM to DSD256.
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Conversion of PCM to DSD is exactly what the original Valvedac does. It is on the first page. The ASRC is not needed for raising the base rate of the PCM input.
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Then perhaps you should do some more research. The raw DSD version was preceded by a PCM input version.
On the first page it says about the original valve dac: "Supports DSD64 and DSD128 by first converting them to PCM."
The it says for the raw DSD version: "Designed for raw DSD; it doesn't need any FPGA or SRC4392, because the raw DSD signal is already a sigma-delta modulate"
Goes on to say: "Yet another approach could be to use an AK4137 board for the conversion from PCM to a sigma-delta modulate, but no-one has tried that yet."
The it says for the raw DSD version: "Designed for raw DSD; it doesn't need any FPGA or SRC4392, because the raw DSD signal is already a sigma-delta modulate"
Goes on to say: "Yet another approach could be to use an AK4137 board for the conversion from PCM to a sigma-delta modulate, but no-one has tried that yet."
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Sure there is a modulator. Does it sound like the one in AK4137? Very doubtful IMHO. Its a different algorithm. Filter after upsampling of PCM is different too.
I am currently building the raw DSD version and plan to experiment with the SAA7350 as DSD source.
The original valve DAC uses an SRC4392 to asynchronously convert signals to 200 kHz sample rate, the rest of the digital signal processing is done with an FPGA board. The whole digital path is as follows:
DSD64 and DSD128: decimated to 201.6 kHz PCM by the FPGA, converted to 200 kHz PCM by the SRC4392, interpolated to 3 MHz PCM by the FPGA and then converted to a 27 Mbit/s sigma-delta modulate by the FPGA. You have a choice between three different algorithms for this last step. The filter used in the first step is one with a short impulse response.
PCM: prefiltered with or without 2 times interpolation by the FPGA (to work around some limitations of the SRC4392), converted to 200 kHz PCM by the SRC4392, interpolated to 3 MHz PCM by the FPGA and then converted to a 27 Mbit/s sigma-delta modulate by the FPGA. You have a choice between three different algorithms for this last step and three different filter types (steep, apodizing or no prefiltering) for the first step.
DSD is a Sony/Philips trade name for a sigma-delta modulate, so in the DSD case, a sigma-delta modulate gets converted to PCM and then back to a sigma-delta modulate. I chose this solution to be able to pass it through the SRC4392 asynchronous sample rate converter.
The reason for using asynchronous sample rate conversion was that I wanted the DAC to be able to synchronize to an incoming signal, as required for S/PDIF, Toslink and AES3 signals, and couldn't make a large enough tuning range with my crystal oscillator.
I haven't a clue if it sounds better, worse or exactly the same as an AK4137.
DSD64 and DSD128: decimated to 201.6 kHz PCM by the FPGA, converted to 200 kHz PCM by the SRC4392, interpolated to 3 MHz PCM by the FPGA and then converted to a 27 Mbit/s sigma-delta modulate by the FPGA. You have a choice between three different algorithms for this last step. The filter used in the first step is one with a short impulse response.
PCM: prefiltered with or without 2 times interpolation by the FPGA (to work around some limitations of the SRC4392), converted to 200 kHz PCM by the SRC4392, interpolated to 3 MHz PCM by the FPGA and then converted to a 27 Mbit/s sigma-delta modulate by the FPGA. You have a choice between three different algorithms for this last step and three different filter types (steep, apodizing or no prefiltering) for the first step.
DSD is a Sony/Philips trade name for a sigma-delta modulate, so in the DSD case, a sigma-delta modulate gets converted to PCM and then back to a sigma-delta modulate. I chose this solution to be able to pass it through the SRC4392 asynchronous sample rate converter.
The reason for using asynchronous sample rate conversion was that I wanted the DAC to be able to synchronize to an incoming signal, as required for S/PDIF, Toslink and AES3 signals, and couldn't make a large enough tuning range with my crystal oscillator.
I haven't a clue if it sounds better, worse or exactly the same as an AK4137.
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Don't know if anyone else here tried it, but I compared CT7302 DSD modulator to AK4137 and I can't tell you bad the 7302 sounded. I tried working with their factory contact, but they didn't seem to understand or care that it was unusably bad.
Regarding the sound of software DSD modulator algorithms, one can easily try some of the various modulators in the trial version of HQ Player. They all sound different.
Thus, I personally doubt that two different modulator designs are likely to sound the same.
Also, DSD only starts to get really good up at DSD256 (or higher). For most DACs a DSD256 modulator must clock out at 11.2896Mhz, or less commonly at 12.288MHz. Don't know about the Tube dac modulator?
Regarding the sound of software DSD modulator algorithms, one can easily try some of the various modulators in the trial version of HQ Player. They all sound different.
Thus, I personally doubt that two different modulator designs are likely to sound the same.
Also, DSD only starts to get really good up at DSD256 (or higher). For most DACs a DSD256 modulator must clock out at 11.2896Mhz, or less commonly at 12.288MHz. Don't know about the Tube dac modulator?
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Please post the measurements so that we would have easier time understanding what you say.
That reminds me that I forgot to mention in post #133 that there is a surprise mode to support randomized ABCX tests, and that you can change whatever you want in the FPGA's processing if you are prepared to rewrite some of the Verilog code.
MarcelvdG,
I understand you worked at Philips, did you work with any of the SAA7350 design team?
I understand you worked at Philips, did you work with any of the SAA7350 design team?