Should have been AKX-22 https://sites.google.com/site/ackodac/modules-and-kits/clocks-and-oscillators
That's just the point I was trying to make, that even though you use well-shielded connectors, you get a relatively high noise floor. Whatever the cause, it won't be the crosstalk issue I initially had with my flatcable. Apologies for mixing up the connectors.
The decoupling is right next to the 74LV574As and the buffers have a force-sense connection (at least with my board layout). @Thorp used an LT304x, so maybe Thorp knows what noise floor you can get that way - although that's again with a different layout, of course.
Regarding balanced connections, I know Hans will disagree, but I would always make them AES-48 compliant unless there is a very urgent reason not to. AES-48 compliant means that XLR pin 1 goes straight to the metal enclosure on both the sending and the receiving sides, so the metal enclosures and cable shield form one big Faraday cage, and the enclosure is connected to the circuit ground at one and only one spot.
I have tested my board a bit more. I get exact same noise from both channels and analog part works without any noise (with 010101 pattern). So I suspect the noise is jitter coming from the clock doubler. Input to 74LVC2G86 has overshoot and output does not look clean. I'll probably add series termination resistors on both input and output to 74LVC2G86. BTW is it possible for 010101 pattern to work well even though clock doubler has jitter?
After having looked at the specs of your ADC, I finally understand your test set up.
Your ADC has dual channels and an amazingly high dynamic range, that’s why you can measure the S/N for a high level input signal without the need for using a LNA.
Very impressive.
Hans
Marcel,
I only partly disagree, because what you describe is what is used in professional equipment.
However in consumer electronics pin1 is always connected to the analog ground on both ends and not to the chassis.
But even with AES-48, both chassis are in most cases already connected to mains ground through their power cable, and if so connecting both chassis through pin1 means an extra connection that can transfer noise from one chassis to the other.
But in the end, the professional connection is way better as the consumer connection.
Hans
Doubler is apparently okay if its only used for the RTZ function. In this case the XO is not doubled before the dac. Instead there is a post-XO exclusive-or gate doubler circuit in the dac for RTZ.
aha, U19, U25and 28, i have to zoom in to be able to read those parts, so I took it for Bohrok`s own doubler circuit, thanks.
U28A is the clock doubler.
The issue with clock doublers is that spectral peaks in the clock at half the sample rate (or its odd multiples) can mix idle tones around half the sample rate down into the audio band. (I mean mix in the RF sense, produce sum and difference frequencies.) Straightforward single-bit sigma-delta modulator algorithms produce quite strong idle tones around half the sample rate, tones that get frequency modulated by the desired signal, in their digital signal spectrum. When you have a crystal oscillator running at half the sample rate and double it, some of the original crystal frequency is bound to leak through, producing a spectral peak at half the sample rate. That peak can then mix down the idle tones. FIRDACs with a notch at half the sample rate mitigate the issue to some extent, as do modulator algorithms that produce little or no idle tones around half the sample rate.
In this case, the clock doubler doesn't go from 1/2 times the sample rate to 1 time the sample rate, but from 1 time the sample rate to 2 times the sample rate. Exact integer multiples of the sample rate are quite harmless, as the digital signal spectrum around multiples of the sample rate is just a copy of the desired audio spectrum.
The issue with clock doublers is that spectral peaks in the clock at half the sample rate (or its odd multiples) can mix idle tones around half the sample rate down into the audio band. (I mean mix in the RF sense, produce sum and difference frequencies.) Straightforward single-bit sigma-delta modulator algorithms produce quite strong idle tones around half the sample rate, tones that get frequency modulated by the desired signal, in their digital signal spectrum. When you have a crystal oscillator running at half the sample rate and double it, some of the original crystal frequency is bound to leak through, producing a spectral peak at half the sample rate. That peak can then mix down the idle tones. FIRDACs with a notch at half the sample rate mitigate the issue to some extent, as do modulator algorithms that produce little or no idle tones around half the sample rate.
In this case, the clock doubler doesn't go from 1/2 times the sample rate to 1 time the sample rate, but from 1 time the sample rate to 2 times the sample rate. Exact integer multiples of the sample rate are quite harmless, as the digital signal spectrum around multiples of the sample rate is just a copy of the desired audio spectrum.
Marcel,
When I try Acko's clocks with Andrea's FIFO buffer, either I can let your dac generate the RTZ or I can configure the FIFO buffer to generate RTZ exactly on XO rising MCLK clock edges. Seems like it might be more precise to let the FIFO do it, or at least try it both ways. What do you think? What would be involved to try it?
When I try Acko's clocks with Andrea's FIFO buffer, either I can let your dac generate the RTZ or I can configure the FIFO buffer to generate RTZ exactly on XO rising MCLK clock edges. Seems like it might be more precise to let the FIFO do it, or at least try it both ways. What do you think? What would be involved to try it?
I haven't a clue what the input signals of U28 look like, but Hans did have a look at the output of U28A on my prototype board, using a 470 ohm resistor, 50 ohm coax cable and 50 ohm termination at the input of his oscilloscope. It looked quite nice, actually, with a pulse width of about 8 ns, closer to the design target than I had expected. When there is a duty cycle error at the output of U29, which there normally is, you do get one somewhat longer clock cycle, one somewhat shorter clock cycle, one somewhat longer clock cycle, one somewhat shorter clock cycle and so on at the output of U28A. That is systematic jitter, but systematic jitter corresponding to tones at integer multiples of the sample rate, which are harmless.
The answer to your question is yes, even with jitter at frequency offsets that would normally be harmful. With a 010101... input pattern, the FIRDAC switches between the patterns 0001, 0010, 0100 and 1000, which all have the same average. Clock jitter then only displaces the switching spikes a bit, which hardly has any impact on the low-frequency content.
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If the purpose is to find out how well or how poorly my DAC works, it seems logical to let my DAC generate the RTZ and the doubled clock.
I can't answer your question about how to hook up Andrea's FIFO buffer to my DAC, because I know nothing about Andrea's FIFO buffer. Is there a description somewhere about what output signals it produces in RTZ mode? What are the high and low levels?
As I see it, it is just a dc servo to null output offsets. U8 is a pure integrator with a Cap in its feedback. So will attenuate dc/low frequency common mode noise but not higher ones. So not the same as a summing differential amp that can block both dc and ac common mode effects. Any further insights into this operation of the circuit🤔
Good point Marcel, yes we need to keep things within scope of the intended plan.
Mark's explanation is fully correct. The loop bandwidth is roughly 1.5 MHz, so common-mode disturbances below 1.5 MHz are suppressed (the further below 1.5 MHz, the better they are suppressed). The only reason why C18 and C45 are in the circuit, is to keep the common-mode loops stable.
Thank you Marcel and Mark, finally making sense to me🙂
So, although this DAC is designed with balanced outputs, but with this circuit in place, utilising just one half of the outputs for unbalanced (SE) drive does not compromise the CMRR with the audio range.
The test setup by Nautibuoy and Mark for unbalanced drive is technically fine
So, although this DAC is designed with balanced outputs, but with this circuit in place, utilising just one half of the outputs for unbalanced (SE) drive does not compromise the CMRR with the audio range.
The test setup by Nautibuoy and Mark for unbalanced drive is technically fine
Thank you, all good in light of the insights gained so far on how Marcel’s DAC prepares the outputs.