Yes, the sensitivity to phase noise is greatest for equal weights in a FIR DAC. You might notice it came last after fixing that part.
Of course. As noted my suggested sequence is:
Dual DAC's interleaved, with suitable filtering
Non-rectangular (personal preference Kaiser) window function
Increased master clock frequency (4X instead of 2X), to allow 75% duty cycle instead of 50%
Thor
The reason for this is quite simple: the four shift register outputs in my DAC are already interleaved. As there is half a bit clock cycle delay between the taps, two adjacent taps together ideally produce the same waveform as an NRZ DAC would produce. In total, there are four taps, also suppressing idle tones near half the sample rate. The schematic looks a bit complicated for a simple four-tap FIRDAC because there is a positive and a negative part and they are interleaved in various ways to improve matching (and thereby reduce data-dependence of the current out of the reference supply).
I tried to explain that to Thor in our private discussion, but somehow the message didn't come through; I'm still not sure whether he didn't understand me or I didn't understand him or both. After I found out that Thor is a manufacturer rather than a hobbyist, I stopped the PM thread; helping hobbyists is no problem, but I don't think my boss would appreciate it if I helped potential competitors.
When reproducing a 10101010... bit pattern, the waveforms for my DAC ideally look something like this:
That is, each 1 in the input signal results in a pulse at positive output 0, each 0 results in a pulse at negative output 0, and those are then shifted with half a bit clock period between the taps.
Of course you can think of more complicated schemes with higher duty cycles, but then you need a higher multiple of the bit clock frequency.
Regarding passive filtering, there are the 8.2 nF NPO capacitors on the DAC board right at the outputs of the resistor networks.
I have thought a bit about making a passive LC filter and terminating it with an MFB stage input, such that the impedance ideally goes to zero at 0 Hz and for high frequencies, but I haven't worked it out to anything practical yet. Without inductors, I could only come up with either the present scheme or solutions of which the impedance is by design not very low at low frequencies. I want the DACs to work into virtual grounds to keep the load on the reference data-independent, among other things.
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"I found out" meaning that he mentioned it in one of the PMs. In retrospect, my response was a bit silly; I'm an integrated circuit designer and Thorsten is not, so we are actually no competitors at all.
With my FIRDAC length, I need equal weights to suppress idle tones around half the sample rate. For much longer FIRDACs, I think unequal weights can result in better suppression of far-off jitter while still producing a notch at half the sample rate, see the attachment.
Yes, BUT... Let's be clear, the topic is this circuit:
It is clocked at 2fs where Fs is the DSD Sample rate, say 2.8224 MHz. Our 5.6448MHz clock will shift one bit for each clock.
If we send NRZ data to this DAC directly, and compare to RTZ here is the result:
Yes, you have multiple taps, but in "zero" part of "return to zero" for a set of 1's rippling through the SR, half of all taps are zero, causing common mode at 1/2 of the shift register clock. It matters not how many taps you have, what would be 1111 / 0000 on the outputs (P / N) with NRZ data sampled at 2fs will be 1010 / 0000 on the outputs (P / N) with RTZ data sampled at 2fs.
Now allow me to add a second set of data delayed by 1/2 BCK.
The second delayed DAC substantially restores the NRZ waveform and common mode, leaving only the glitches caused by unequal rise and fall time as common mode, at 2FS.
But they cannot, they are fed a RTZ waveform, meaning two adjacent taps must be 01 or 10 for a 1 and 00 for a zero, where NRZ would show 11 / 00.
Only my suggestion of introducing actually a second DAC with data delayed by 1/2 FS (or 1 SR CK) produces this "same waveform as an NRZ DAC".
Yes.
And I suggested that simply taking the feed of the second DAC from the first Tap on the first DAC, which is cut and jump on most PCB's, would in fact create this "equivalent to NRZ DAC" but as you rightly pointed out, it would create a small amount of disturbance on the reference voltage.
How material on a 4-Layer PCB with ground and power planes and proper decoupling is matter of debate though. It did however lead to another
I understood quite well, you are very clear in your explanations. It is no doubt may failing not making points understandable.
Alas, I am a private individual, not a manufacturer. But I am a consultant for hire and indeed have a DAC project for a customer. However a straight copy of a DSC2 or your DAC would have been fine for that.
My reasons to discuss my suggestions and ideas with you were more in the spirit of enquiry to gain knowledge and perhaps give a few ideas you may have overlooked. An exchange between professionals in the interest of knowledge. I am sorry this was misunderstood and would again like to thank you for your time. It is quite embarrassing for me that was not able in our conversation, to contribute anything you found of value.
Something like this but NOT EXACTLY LIKE THIS. See above.
It is easy to simulate.
In many cases 1024 X Fs (where Fs is 44.1/48kHz) is available in modern digital audio systems.
Well, I see these as part of a MFB lowpass, formed of the input stage of the "Filter" and the DAC's effective Z-Out.
As such it is not really passive filtering.
Inductors are available at sub Ohm DCR, why the prejudice against inductors?
If the DCR of our inductor is low enough.... Is there really such a huge difference terminating a DAC into an active inverting input or into such an input with (say) 250mOhm series resistance?
Thor
It is entirely my fault, I should have mentioned it upfront.
I was instead echoing that Carly Simon song and that 90's dance track by Culture Beat, being Mr. Vain and "so vain", to presume that my name and person (and that fact that I have worked professionally in audio) were generally known in the scene and did not need explicit statement, nor did I feel was that particularly relevant.
Thor
Maybe you should simulate my DAC, then you will finally see how it works - specifically that half the taps form your second DAC.
I have no problem with inductors, in fact I have potcore inductors in my valve DAC. The trick with an LC filter would be to terminate it without adding substantial series resistance (which would worsen the virtual ground at low frequencies) or shunt conductance (which would add noise). I think a combination with an MFB stage could do the trick.
Marcel, your DAC gets two RTZ Data, SD(P) and SDN.
Both Data is forced to zero for 50% of the time, regardless of state. That is what RTZ means. The "forced zero" state lasts one clock cycle of the shift register clock and thus 1/2 of the nput BCK.
It means if there is always a "gap" of 1 shift register clocks between two sequential 1's applied to the shift register.
As data and clocks have simple parallel connections, without any delay between them, these forced zeros ripple through the shift register and cause the large levels of CM noise (and a 6dB loss in signal strength and thus SNR).
Your definition of "interleaving" and my one are very different. To me "interleaving" in an RTZ DAC means we use a second DAC running delayed thus that the "1" from the second DAC "fill in" the Zeros caused by RTZ on the output of the first DAC and visa versa.
This is NOT the case in your DAC. And it creates a large problem with common mode noise at BCK.
I did simulate it but did not keep that file as I kept evolving things. If and whem I find time I will recreate the full sim of your DAC logic to illustrate what I mean.
Thor
For Marcel's dac there are both RTZ zero (0's) and inverted RTZ zeros (1's) rippling through the same shift register IC. For that reason, in terms of things like Vref loading and shift register IC ground bounce, the shift register data is interleaved.
However from the perspective of the output stage, the I/V opamps see RTZ zeros (either inverted or non-inverted) in the data. So from the perspective of the I/V opamps the data is not interleaved.
Does that more or less sum up the interleaving arguments?
However from the perspective of the output stage, the I/V opamps see RTZ zeros (either inverted or non-inverted) in the data. So from the perspective of the I/V opamps the data is not interleaved.
Does that more or less sum up the interleaving arguments?
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Love this stuff... if only I can begin to understand it... baby steps... thanks Thor and Marcel...
In looking at I/V converters, transients look problematic if they exist. IME complete controlled transitions can be ignored, as representing fixed RMS highs and lows being cancelled (becoming only an artifact of the nature of the digital stream). Truncated transients appear unpredictable though they may not be in representing some form of consistent RMS artifact. It depends on how well any transients can be handled.
In looking at I/V converters, transients look problematic if they exist. IME complete controlled transitions can be ignored, as representing fixed RMS highs and lows being cancelled (becoming only an artifact of the nature of the digital stream). Truncated transients appear unpredictable though they may not be in representing some form of consistent RMS artifact. It depends on how well any transients can be handled.
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Look at the input data. Input Data is NRZ.
First, data is reclocked and split into two polarities per channel at the output of the second xx74.
Now we have two sets of Data with opposite polarity. In a system with a suitable master clock present this could BTW simplified a lot, here it helps reliably bridge clock domains.
We then use bunch of Or-Gates with the XOR gate U28B to insert zeros. The XOR gate has one input at VCC and the other at BCK:
This way the output will become "L" when BCK is "H" and "H" when BCK is "L". An inverter would pretty much do the same, but there are some possible niceties around timing.
Our four data streams pass through four Or Gates, which all have one input tied to the inverted BCK.
The OR gate is simple. As long as one input is L, the output is L.
This means whenever BCK is H after the edge has been delayed by the XOR Gate and the switching time of the OR gate(s), the output for all four data streams IN COMMON is forced to Zero, regardless of input data..
Whenever BCK is L the output of the OR Gates will be whatever the input is. During this half BCK clock, one output will be L and the other must be H.
Finally the data at the outputs of the OR Gate(s) is delayed using RC and sampled by a set of D-Flip-Flops (aka Latches) and is inverted into the bargain. This will sample at the leading edge of the doubled clock and will thus have capture both the "zero" section (which becomes H ) and the "data" section of the cycle.
The clock from these comes from the clock doubler (or a phase and frequency locked MCK of 2 X BCK) which uses an XOR gate double the clock.
The same clock then also drives the DAC. The DAC is dual-4 Bit FIR.
However, there is no time domain interleaving (e.g. invert clock polarity to one of the DAC or delay the data one DAC by 1 shift register clock.
This that on the first clock we write all H into all four data lines to all four shift registers. This is the common mode part, because, because all four data lines have the SAME state.
We then in the clock cycle write the actual data part into the shift register which complementary, that is if one line is L the must be H.
This generates our differential mode signal.
The result is a classic RTZ FIR DAC. It is covered extensively in uses at RF, as the output spectrum of aliases differs from NRZ considerably and useful for system that suppress the base band and actually use alias products as a signal at frequencies much higher than actual base band of the DAC.
For audio this behaviour however is NOT A GOOD THING in my book.
In other words, we solved Inter Symbol Interference (ISI) distortion. This is commonly H2 dominant with higher even order products and will be suppressed for the even orders and cause increased odd distortion in a balanced NRZ FIR DAC (e.g. Pavel Pogodin DSC2) but not in a SE FIR DAC (e.g. Jussi DSC).
But we created a new problem (actually several).
As said, my main mitigation strategy would be to double the DAC again and feed it with a signal delayed by one SR clock.
Or indeed give up the extreme symmetry of MvG's original design (which will give MAYBE more modulation of the reference supply by audio) and instead of feeding U9/U16 from the same data as U7/U14 feed them from Q0/Q1 of U7/U14 to achieve time domain interleaving.
Doing that in turn reduced the common mode noise from in effect the bit clock at full Vcc of the shift registers to that caused by the difference in rise and fall time at each edge of BCK, resulting in much less energy to filter out to prevent it from causing havoc downstream.
And in doing so, we also restored the effective waveform (minus the glitched at the clock edge) to an NRZ one. Again, this is quite well covered in literature on RF DAC's (and ADC's), where we can also find options that go beyond simple interleaved RTZ DAC's.
I had originally actually written to MvG to suggest the "cut & jump" interleaving when there was a lot more development ongoing, but as said, the idea did not "fly" with Marcel, for whatever reason. The larger discussion grew out of that up to the abrupt end.
I hope this clarifies what I am going on about and how it relates.
Thor
Yes, see post #2266, https://www.diyaudio.com/community/threads/return-to-zero-shift-register-firdac.379406/post-7621479 In this example, the sum of the positive outputs is constant and the sum of the negative outputs is constant - except for glitches due to unequal rise and fall times, of course.