Hello all, I just finished my power supply build (using the group buy kit). Unloaded, I’m measuring 26V at the power supply output, which seems rather large. I checked all values 3 times and measured every resistor. My wall voltage is 125-126V. Any thoughts on where I need to look to see why I’m a bit high on the voltage? My caps are 25V and I don’t want them to break down, so it’s off for now. Thanks!
How about using a more expensive SMU or VNA for measurements, is that okay?
Obsessing about measurement and selection of parts is part of the DIY fun.
People will obsess, fortunately for me, I don't have the chops and I have faith that @wayne did enuf obsessing for all but the most OCD! 😉
oh yes, but pretty much all things of importance covered few times in 1700++ posts
besides, some things based on self-obsession are usually (best) performed in solitude
I ran a PSUD sim, 18Vac at the transformer secondary (unloaded), 10M load at the output. Get 24Vdc with 117V PT input, adding that line voltage could be 126Vac that makes the output voltage 26Vdc (no-load). Putting the load on the PS should bring it in spec.
With pencil and paper, you can solve for the CCS resistor value, if you know the JFET's Vpinchoff and IDSS.
One method of solution would be plain old algebra, and another {a lot more fun!} approach is graphical. Plot Ids versus Vgs, and overlay the resistor I-vs-V curve. Presto, the intersection of those two curves is the operating point. No math!
If you're hoping to achieve a certain specific current for your CCS, locate that current on the JFET curve and draw a straight line from that point to the origin. Presto, the slope of the straight line is (1/R). Easy.
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One method of solution would be plain old algebra, and another {a lot more fun!} approach is graphical. Plot Ids versus Vgs, and overlay the resistor I-vs-V curve. Presto, the intersection of those two curves is the operating point. No math!
If you're hoping to achieve a certain specific current for your CCS, locate that current on the JFET curve and draw a straight line from that point to the origin. Presto, the slope of the straight line is (1/R). Easy.
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I need to ask a "stupid" question about JFET Pinch off definition. Even if you find it very irritating.
Vp is the Vds value where the current "saturates". Above Vp Id does not change much even if Vds raises a lot?
Vp is not the value of Vgs where Id is almost zero? ....that value is called Vgs_off?
In my case with my J112's Vgs_off is measured to -3.8 V (Id is here 4.8 uA....so almost zero). Maybe it will never turn off completely. Value are from the cheap Peak instrument. I have no very expensive transistor measuring equipment.
So in MJ's equation it is Vgs_off I need to know (-3.8 and -3.6 for the other J112)?
Thank you very much for the equation and graph. I have copied it to my Pearl3 folder on my PC where I collect documentation.
Think I can isolate R from the equation.
Vp is the Vds value where the current "saturates". Above Vp Id does not change much even if Vds raises a lot?
Vp is not the value of Vgs where Id is almost zero? ....that value is called Vgs_off?
In my case with my J112's Vgs_off is measured to -3.8 V (Id is here 4.8 uA....so almost zero). Maybe it will never turn off completely. Value are from the cheap Peak instrument. I have no very expensive transistor measuring equipment.
So in MJ's equation it is Vgs_off I need to know (-3.8 and -3.6 for the other J112)?
Thank you very much for the equation and graph. I have copied it to my Pearl3 folder on my PC where I collect documentation.
Think I can isolate R from the equation.
Erno Borbely's JFET articles are still alive on the web. https://audioxpress.com/article/JFETs-The-New-Frontier-Part-1
and https://audioxpress.com/article/JFETs-The-New-Frontier-Part-2
Ok, but it is very confusing that there are different definitions of the same. If you Google JFET Pinch off you will see definitions of Vp (even in Wikipedia) defined same as what Borbely calls Vsat. Logical Vsat is a better name and Pinch off a better name for where Id is almost zero. It is easier to understand if definitions are clear especially when you are in a learning phase. My cheap instrument is probably not able to measure 0.1 uA to measure the real pinch off (PEAK calls it Vgs_off which also is a nice understandable name).
R27 = 1k results in 3.2V for JFET 1 and 3.3V for JFET 2. So 3.1 - 3.2 mA.
I used my lab supply and with 1k the breadboard circuit seems very stable from 7V to 20V with almost no change in Id.
So 1k will be my choice for R27. I even have 1k RN55.
I used my lab supply and with 1k the breadboard circuit seems very stable from 7V to 20V with almost no change in Id.
So 1k will be my choice for R27. I even have 1k RN55.
Hello All,
By my measurements I did not find a clear point that could be identified as JFET Pinch off or cut off. Each of the Jfet's that I looked at had a smooth tapering curve that approached a minimum current.
Pinch off is part of the text book theory that is not borne out by the measurements but close.
DT
See PF5102 measurements as an example:
In this document the pinched-off is explained for a JFET at page 342:
https://www.cet.ac.in/wp-content/uploads/2023/01/Part-V-FET.pdf
"As VDS is increased gradually the depletion layers at the drain end of the channel just meet together, reducing the effective channel thickness to zero. This condition is called pinch-off. Under this condition the drain end of the channel is just pinched-off. The pinch of voltage (Vp) of a JFET is the voltage between the drain end of the channel and the gate at the onset of pinch off. It is also equal to the minimum reverse bias between drain end of channel and gate at which the channel thickness become zero at the drain end. The voltage between the drain-gate p-n junction at pinch off may be expressed as Vp = V0 + VD(sat) - VGS"
This is a more clear definition of Vp.
I think that is more correct than the other article where it is used as Vgs_off.
Vgs_off is a theoretical value as the JFET never stops conducting. Then a minimum current has to be defined in order to define Vgs_off.
https://www.cet.ac.in/wp-content/uploads/2023/01/Part-V-FET.pdf
"As VDS is increased gradually the depletion layers at the drain end of the channel just meet together, reducing the effective channel thickness to zero. This condition is called pinch-off. Under this condition the drain end of the channel is just pinched-off. The pinch of voltage (Vp) of a JFET is the voltage between the drain end of the channel and the gate at the onset of pinch off. It is also equal to the minimum reverse bias between drain end of channel and gate at which the channel thickness become zero at the drain end. The voltage between the drain-gate p-n junction at pinch off may be expressed as Vp = V0 + VD(sat) - VGS"
This is a more clear definition of Vp.
I think that is more correct than the other article where it is used as Vgs_off.
Vgs_off is a theoretical value as the JFET never stops conducting. Then a minimum current has to be defined in order to define Vgs_off.
Some people simply perform computer searches (using nonlinear optimization algorithms) to find the unique set of coefficients for the SPICE model, which gives the best fit / lowest sum-of-squared-errors, between simulation and measured data from actual physical devices. Then (Best Fit Vpinchoff) is used as a proxy for "Vp", (Best Fit Idss) is used as a proxy for "Idss", (Best Fit Lambda) is used as a proxy for "Lambda", etc.
This isn't an especially quick or easy procedure, because you first must gather and measure a population of JFETs, then (the really difficult bit) decide which of them is the "typical" device, whose model coefficients you want to extract by numerical fitting. There's a lot of unit-to-unit variation between JFETs having identical part numbers, even from the same reel or ammo-pack of parts, and you want your model parameters to represent the population as a whole, as best as possible. So it's crucial to pick a truly representative part as your "typical".
Notice that you don't actually measure a quantity called Vpinchoff (or Idss or Lambda or ...) on a real transistor; instead you ask computer software to solve for Vpinchoff which gives the best match between model equations (in SPICE) and measured data in the real world.
Another, more controversial, approach is to completely forget "typical" devices and focus your modeling efforts upon "worst case" parts. The idea is, if your circuit works correctly even with worst case devices, it will also work correctly with the entire population. Pessimists only receive pleasant surprises is the mantra.
An example of the JFET worst case modeling approach, is in (this) old thread from 2016.
This isn't an especially quick or easy procedure, because you first must gather and measure a population of JFETs, then (the really difficult bit) decide which of them is the "typical" device, whose model coefficients you want to extract by numerical fitting. There's a lot of unit-to-unit variation between JFETs having identical part numbers, even from the same reel or ammo-pack of parts, and you want your model parameters to represent the population as a whole, as best as possible. So it's crucial to pick a truly representative part as your "typical".
Notice that you don't actually measure a quantity called Vpinchoff (or Idss or Lambda or ...) on a real transistor; instead you ask computer software to solve for Vpinchoff which gives the best match between model equations (in SPICE) and measured data in the real world.
Another, more controversial, approach is to completely forget "typical" devices and focus your modeling efforts upon "worst case" parts. The idea is, if your circuit works correctly even with worst case devices, it will also work correctly with the entire population. Pessimists only receive pleasant surprises is the mantra.
An example of the JFET worst case modeling approach, is in (this) old thread from 2016.
