MPP

The IF3901 is like a pink elephant or a unicorn if you wish.
Can not wait until you get some Stefano.
The CSS has to provide THE EXACT SAME CURRENT THEN THE INPUT STAGE PROVIDES AT IDDLE, ALL THE TIME. If that does not happen the DC voltage at the output node is not EXACTLY at 1/2 voltage of the supply. That condition gives the MAXIMUM DYNAMIC RANGE ( Tietze- Schenk ).

I am also thinking that with one monolithic i.e. one pair of IF there should be plenty of gain, very low noise more thermal stability due to the monolotic.

I was also thinking why wouldn't we use Jfet for the current source?
In this instance using the same paralled IF monolithic?
Is it a stupid idea?
 
here is the idea I was describing before.
It onlu gives 46dB gain which is clearly not enough.

The problem however is:

1) the noise simulation shows 0.87nV/rtHz for only 46dB which puts it into the noisy side
2) the topology is INVERTING and I don't think there is much it can be done here. I would have expected that since output is sourced from a common source

Another thing that needs to be noted and that I just thought of is that output of the first stage can't be half of the rail, this wouldn't lead to maximum headroom, but has to be rail-Vcascade-2V(for saturation) which clearly shows that for good headroom capability you need high voltage rail which migh be a problem for regular JFets or at least operating to their maximum derating.
 

Attachments

  • sim-3.jpg
    sim-3.jpg
    114.4 KB · Views: 285
I really do not know, but if I was guessing I would go like this, the larger the mosfet the better 🙂 in actual fact a large (hexfet) mosfet is a matrix of paralleled fets and thus the more in parallel the better. Thus I think the larger the dye the better. Just my guestimate! You know where to send that bottle 🙂

Some research and I found:
The current path is created by inverting the p-layer underneath the gate by the identical method in
the lateral MOSFETs. Source current flows underneath this gate area and then vertically through
the drain, spreading out as it flows down. A typical MOSFET consists of many thousands of N+
sources conducting in parallel. This vertical geometry makes possible lower on-state resistances
(RDS(on)) for the same blocking voltage and faster switching than the lateral MOSFETs.

In http://www12.fairchildsemi.com/an/AN/AN-558.pdf

The number of parallell fets is 'many thousands' 🙂
 
Last edited:
For two days we have hard snow here.... My vehicle decided to stall... I have been updating my automotive knowledge... after verifying the fuel pump does produce enough pressure to the rail, I got a clue from a friend and focused myself in the electric circuit.... finally found the issue... bad ignition coil... Today, another highly stressed morning... had to climb a hill to borrow a car from another friend... transport kid and wife to the plain, go shop for a coil, get back, replace the coil... car starts... loose fixing nuts... go to garage, borrow magnetic tool, find nuts... fix everything... One of my students gave up classes.... today is payday... lots of €€ transfers... barely enough... so no time for pushing you guys 🙂
 
that's the good spirit Ricardo!!!! 🙂

Now to comment on some progresses I made on the design, do you guys still remember the one shot approach?

I modeled it up as it seems to be a pretty nice circuit.
it can be easily obtained 62dB out of it, non-inverting topology.
However Noise simulation would seem to rule this out. Below is the noise simulation's result.
Residual noise would be comparable to a modified paradise without ElCap which sounds wonderful, but IMHO noise is unacceptable.
Some reasonable noise level could be 0.7nV/rtHz.

Any comment? Is it possible to fix this?
 

Attachments

  • sim-oneshot.JPG
    sim-oneshot.JPG
    188.6 KB · Views: 227