On the face of it this may work: analog.com/static/imported-files/data_sheets/AD8605_8606_8608.pdf Power bandwidth exceeds 10 MHz, its full rail to rail in and out etc. The noise is a little higher that your spec and its 5V supply. Settling time is listed as less than 1 uS.
Clamping amp- Here is a reference- http://www.analog.com/static/imported-files/application_notes/706710305AN256.pdf Essentially you have a back to back pair of hot carrier diodes limiting the input to a narrow area around 0V or wherever you set the reference. it could kick back some nonlinearities however since the diodes will change the load abruptly if its not isolated.
I am guessing that you are capturing the peak by reading the peak number from the ADC. If they are time stamped you could get the frequency as well. With that you don't need much outside of the target range (+/-10% perhaps) to get very precise level data. Once you have the peak voltage and the rep rate you don't even need to look at all the samples, just those around the target time and amplitude. With that you could steer both the frequency and the amplitude pretty easily with the "mdac".
I suspect there is a way to trick this into working: LTC6957 - Low Phase Noise, Dual Output Buffer/Driver/Logic Converter - Linear Technology since its a linear device designed not to saturate when it clips and is usable to 100 MHz but its way "off label prescription" use. I intend to try it for various digital applications anyway so I'll see if I can get it to work in the analog region. I won't have samples or time for a while so don't wait for me.
And this new gem: LTM2883 - SPI/Digital or I2C ?Module Isolator with Adjustable ±12.5V and 5V Regulated Power - Linear Technology could be a one stop solution for a number of isolation problems.
I'm using this DSP1N5D17 Power-One | 179-1079-ND | DigiKey on the QA400 interface. It runs at around 330 KHz. Its pricey ($17) but seems to work pretty well and provides an isolated split supply.
What about boot-strapping the opamp via PS to +/-24 or what ever... avoiding the rail to rail or sticking etc issues??
-RNM
It not that complicated. The zero crossing of the quadrature is detected and a conversion is started which samples the peak of the zero phase. Just like any analog THSH. The ADC has built in SPI and internal clock. It contains all the glue logic for SPI transfer. The Mdac is loaded directly from the ADC. The I/V convertor is biased to 50% and the output is a proportional signal +/- of the ADC input range 0-5V. The Mdac is referenced with 10V therefore the proportional signal is +/- 5V
What's the oscillator operating level and desired frequency flatness? Even if it's just 1 Vrms, a 100 mVrms error from 10 Hz to 100 kHz is not even a single dB deviation. You can easily figure out a RC network to reduce this error to a fraction of a dB, which then quickly rises the question of measurement accuracy.
The excess distortion you're observing looks like a layout effect--under clipping, the opamp probably draws heavy current. Good layout practice should eliminate the crosstalk to the main oscillator sections.
That sounds like a very interesting part--which is it?
Samuel
Hi Samuel,
The ADC is an LTC1609 200ksps switches capacitor SAR with SPI.
The Mdac is an AD5543 followed with an LT1468 for an I/V convertor.
The layout is good, top ground plane. You mean I should put it all in a grounded metal case, shorten the board to board wires and get a decent power supply? Maybe I chasing a phantom problem that doesn't really exist.
Okay. I'm fussy and am going after at worse a 0.5 db range error. I think with what I have it should be better than this. I hadn't considered the cross talk. Been to focused on other things.
These are two separate boards, SVO and AGC
The output is 3Vrms. I do think I need some buffers between SVO and the AGC board.
I'm really pushing it for load on the SVO. The op amps in each section have 100 ohm isolation resistors right at the output pins and this make the SVO a bit sensitive to loading. Of course with loading the currents go up and so does the crosstalk.
All the op amp buffers / conditioner are inverting mode and I like lower R values to keep the noise down. I thought 5k and 10k R in was reasonable.
Did you also try the LT1037 by any chance?
Here's some info from the hard-core S & H guys -->
"Good results with LME49990 and OPA228.
Also, "If you want to do really fast sampling use a 2 stage preamp.
In some cases you can help overdrive recovery with a diode across the feedback R."
Here's some info from the hard-core S & H guys -->
"Good results with LME49990 and OPA228.
Also, "If you want to do really fast sampling use a 2 stage preamp.
In some cases you can help overdrive recovery with a diode across the feedback R."
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BTW If you're still looking for a USB isolator: just $23.00: Teralink ADuM4160 USB Isolator board
Ohh and yes, they also have aluminum knobs for $0.06 (!), made from: ... drum roll... Aviation grade Aluminum ;-)
http://www.ab-system.hk/index.php?route=product/product&path=85&product_id=282
jan
Ohh and yes, they also have aluminum knobs for $0.06 (!), made from: ... drum roll... Aviation grade Aluminum ;-)
http://www.ab-system.hk/index.php?route=product/product&path=85&product_id=282
jan
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Given the load sensitivity of the SVO. I think I need to buffer with non inverting stages.
The multiplier is already putting a quite a load demand on the BP output and dropping more load on the LP output is just a bit too much. I can see the AGC having to correct for varying loads. Clamping puts an uneven load on the output.
And it even comes in easily hand-solderable SOIC! Great, I'll keep that in mind for the distortion analyzer section.
I can't judge the details, but your description reads like there is a chance for trouble. Think about what currents flow into the ground plane, and how they return to the power supply. With most peak level detectors, there is significant current (dozen of mA) with very high harmonic content (THD possibly several dozen %) dumped into ground. If this current is allowed to flow through the main oscillator section, there's little chance that this would not result in drastic THD increase (even if this path is a solid low Z ground plane). My first dual sample-and-hold board years back introduced nice short spikes in the distortion residual of the oscillator output--perfectly aligned with the timing signals of the two sample-and-hold stages, and orders of magnitude higher than any other distortion source.
There are several means how you can avoid this trap (in order of importance, as far as I can tell):
* Good placement of the various oscillator subcircuits. Place the level detector between main oscillator circuitry and power supply entry. This will reduce the common return impedance coupling as the level detector return current will tend to flow back directly to the supply, and thus doesn't touch the main oscillator ground plane section.
* Use a local shunt supply for the most offensive sources (often the timing generators)--e.g. the AP System One uses an extra resistor-5 V zener-cap supply for the level detector logic rather than the already available 5 V rail. I recall that the SG505 has some heavy RC filtering in the peak detector as well, which is effectively some sort of AC shunt supply.
* Use ground plane slots to form individual return current sections. Of course no signal/supply trace may cross the slot.
There's of course also capacitive and inductive crosstalk going on, but with sufficient spacing this should not be drastic, usually.
Samuel
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I noted you mentioned two stages so I am sure you understand the difference, but for the others allowing more acquisition time reduces the surge currents.
"My first dual sample-and-hold board years back introduced nice short spikes in the distortion residual of the oscillator output--perfectly aligned with the timing signals of the two sample-and-hold stages, and orders of magnitude higher than any other distortion source."
Almost every track and hold oscillator I have measured showed some of this transition. It can also come from the small change in the DC out of the S&H into the multiplier as well.
My AC calibrator gets exceptional amplitude accuracy even though it bypasses the S&H+T&H for the 100KHz to 1MHz band. They felt it was not necessary for that band. Its really only necessary for lower frequencies.
Almost every track and hold oscillator I have measured showed some of this transition. It can also come from the small change in the DC out of the S&H into the multiplier as well.
My AC calibrator gets exceptional amplitude accuracy even though it bypasses the S&H+T&H for the 100KHz to 1MHz band. They felt it was not necessary for that band. Its really only necessary for lower frequencies.
I concur. I had a problem with the cap charging current in multi-phase rectifier, specifically voltage drop of charging current on ESR and PCB trace impedance.
Let me throw some silly idea. If the VCA and second S&H are stable enough (placed in the oven) and other components are stable as well, I prefer to disconnect first S&H from the second one. I don’t care if the level will drift slightly. If the level drifts substantially, window comparator will reestablish connection between first S&H and the second one. This the output level will return to correct value and then the loop will break again. PID controller of dynamic system with hysteresis.
Let me throw some silly idea. If the VCA and second S&H are stable enough (placed in the oven) and other components are stable as well, I prefer to disconnect first S&H from the second one. I don’t care if the level will drift slightly. If the level drifts substantially, window comparator will reestablish connection between first S&H and the second one. This the output level will return to correct value and then the loop will break again. PID controller of dynamic system with hysteresis.
If you look at the droop specs the S&H will need refreshing pretty often. Probably faster with higher temperature.
There is no reason why the AGC even needs to share much of a ground with the oscillator. A differential input monitoring the reference output node should be all that is necessary to get the level to the detector circuitry. For this application you need two, one for each phase to capture the zero crossing to trigger the sample. For absolute accuracy you may need adjustments to align the sample pulse with the peak. If its late or early there will be a drop as the frequency increases.
There is no reason why the AGC even needs to share much of a ground with the oscillator. A differential input monitoring the reference output node should be all that is necessary to get the level to the detector circuitry. For this application you need two, one for each phase to capture the zero crossing to trigger the sample. For absolute accuracy you may need adjustments to align the sample pulse with the peak. If its late or early there will be a drop as the frequency increases.