Keep registering lower current in the lower half... is it normal ?
Plot I(R17)-I(R16) and all will be revealed 🙂 also DO NOT USE THAT HIGH A BIAS (it's not improving anything (except global warming 🙂)). What you see is the non linearity of the OPS (output stage) due to class A operation (but not in a positive way) the + side compensates for the - side (so to say) and the other way around. The sum (or difference) of the currents shows the signal (not each of the currents).
I must say there are some compromises here..... difficult to use use another psu... can I keep the lovely 103 +-35v psu ?
Can I use other trannies (other than BC546/556) ?
2sa970/2sc2240 for instance 🙂
2sa970/2sc2240 for instance 🙂
Like here.
Attachments
Hey Golden Titian Top, whats with .ASC files???😡
You trying to keep us elderly lightweight Mac guys out of it???

You trying to keep us elderly lightweight Mac guys out of it???


2sa970/2sc2240 for instance 🙂
Change Q6 and Q12 also (Vce is borderline)
Can I use 2sa970/2sc2240 for Q6 Q12 ?
Where can I find the Toshibas ?
Can I use 2sa970/2sc2240 for Q6 Q12 ?
Where can I find the Toshibas ?
Yes you can!
In my transistor box 🙂 [I did get a few 100 of each from eBay]
Hey Golden Titian Top, whats with .ASC files???😡
You trying to keep us elderly lightweight Mac guys out of it???![]()
And for those who can't 🙂
You could install Wine http://wiki.winehq.org/MacOSX]
Or use parallels ]Run Windows on Mac - Windows and Mac side-by-side with Parallels Desktop 9 for Mac - Parallels
Or just miss the fun 🙁
Or get a real PC 😉
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So when the bias resistor is 165 Ohm R1, R2 are 115 Ohm ?
I do not see any Miller cap in this design.
Is the circuit stable without it ?
I do not see any Miller cap in this design.
Is the circuit stable without it ?
Thanks for the attachment FdW.
I won't have any Windows stuff here … being Irish anything like that is just too complicated.and when I did have a PC it was always a system problem which caused havoc! 😉
I won't have any Windows stuff here … being Irish anything like that is just too complicated.and when I did have a PC it was always a system problem which caused havoc! 😉
So when the bias resistor is 165 Ohm R1, R2 are 115 Ohm ?
I do not see any Miller cap in this design.
Is the circuit stable without it ?
i did not yet test for stability, has to be done yet.
So when the bias resistor is 165 Ohm R1, R2 are 115 Ohm ?
I do not see any Miller cap in this design.
Is the circuit stable without it ?
R1/2 need more work.
Sure. I arived at 115 Ohm because that gave the best thermal stabily.
I used an amplified diode though in my prototype and not the transdiode string.
The transdiode idea came later but was never build, only simulated.
I used an amplified diode though in my prototype and not the transdiode string.
The transdiode idea came later but was never build, only simulated.
Well, the transdiode thing works (very well indeed).... will now wait for r1/2 and thermal tests on the improved FdW version 🙂
Stability plot, the amp needs a 10p capacitor for compensation. The OpAmp has been changed to a LME49710
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I am using the 49710 opamp... but with 100p miller cap.... this is a good sign.....
Now, why do you use three transdiodes and not only two and increase the bias resistor a little bit ?
And here is something special indeed: Krylov - Bach - Toccata and Fugue - YouTube
This guy (Sergej Krilov) might as well be the highest violin player alive 🙂
Now, why do you use three transdiodes and not only two and increase the bias resistor a little bit ?
And here is something special indeed: Krylov - Bach - Toccata and Fugue - YouTube
This guy (Sergej Krilov) might as well be the highest violin player alive 🙂
I am using the 49710 opamp... but with 100p miller cap.... this is a good sign.....
Now, why do you use three transdiodes and not only two and increase the bias resistor a little bit ?
actually 10p (not 100p)
Still working on that, bias generators are a PITA 🙂 (and the 3-trans-diode version works not bad)
Many thanks.
What is the frequency response ( -3dB ) with this setup.
Soon ... 🙂 I need a bit of time
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