I managed to sim this amp (file from post #72); few observations:
a) Idle current of the OS 360mA. Is that what you wanted? So high?
b) Q5 dissipating 186mW. You need bigger transistor for VAS (e.g. BD139C). Small plastic transistors (e.g. 2n5401) are good only for 100mW.
c) There is huge DC offset at the output of the amp (1.4V). This will skew ALL simulated measurements (Thd, Slew rate, etc).
You need to bring this offset to 0 by adjusting R4/R5. Once it's 0V, then we can continue sims.
BUT - this signals a bigger problem - how are you going to control this offset in a real amp? A pot in the emitters of Q2/Q3 is not a solution, because
this offset will drift with the temperature. You will trim the pot to achieve offset 0mV, and 10 minutes later when you measure it, it will NOT be 0mV....
If it drifts only +/- 20mV that's OK, but we won't know until it's built 🙂 If it drifts more, that's not good....
You need a current mirror in collectors of Q2/Q3 to improve the offset. See Rod Elliott's P101 amp for an example.
Actually P101 is very similar to your amp, except it's using lateral fets.
d) base resistors 10 ohm (at darlington's bases) are slowing this amp even further. My guess is they are not needed at all. Base resistors
are normally used if you want to slow down the OS. This OS is already slow enough 🙂
e) Seems like C11 (100pF) and CFB2 (12pF) values are too high, and also slowing down this amp.
I tried values 33pF and 5pF.
With all these small changes I got 12V/us slew rate, which is fine for small power amp.
The values of C11/CFB2 should be a result of the square wave simulation and stability (phase/gain margin) sims, and should be as small as possible,
while keeping amp stable (phase margin 50 or more), and square waves decent.
Not sure if you did open loop gain (stability) simulation; by looking at the schematic it looks it wasn't done.
Perhaps these values 33p and 5p could go even lower if phase margin allows for it.
f) simple amp like this, should be very stable, and should not need LR network at the output (for the sim).
The ideal is to sim without it, and make it stable and squares looking decent, and AFTER that add LR.
Good amp (unless it's very cutting edge) should work in the sim without LR.
If you can't make it stable in a sim without LR, it's a sign of future troubles in real build.
My sim attached, along with models.
Edit - I noticed another anomaly - your idle current control (adjusting RV1) doesn't work at all. As it is, with 82R, upper darlington has
366mA idle current, and lower one 6.5mA.
It's never gonna work like this. They have to more or less equal.
I suspect that you need to adjust R12/R13/RV1 to achieve symmetrical idle current.
This is also skewing all the simulated results, and might be the reason for the big output DC offset.
If you change R12/R13, it will affect VAS current, so you may need R21 adjustement as well. VAS current should be kept where it is now, 10-13mA.
So it looks like there is still a lot of work to make this amp working correctly.
Don't worry about the Thd values until these issues are addressed 🙂
a) Idle current of the OS 360mA. Is that what you wanted? So high?
b) Q5 dissipating 186mW. You need bigger transistor for VAS (e.g. BD139C). Small plastic transistors (e.g. 2n5401) are good only for 100mW.
c) There is huge DC offset at the output of the amp (1.4V). This will skew ALL simulated measurements (Thd, Slew rate, etc).
You need to bring this offset to 0 by adjusting R4/R5. Once it's 0V, then we can continue sims.
BUT - this signals a bigger problem - how are you going to control this offset in a real amp? A pot in the emitters of Q2/Q3 is not a solution, because
this offset will drift with the temperature. You will trim the pot to achieve offset 0mV, and 10 minutes later when you measure it, it will NOT be 0mV....
If it drifts only +/- 20mV that's OK, but we won't know until it's built 🙂 If it drifts more, that's not good....
You need a current mirror in collectors of Q2/Q3 to improve the offset. See Rod Elliott's P101 amp for an example.
Actually P101 is very similar to your amp, except it's using lateral fets.
d) base resistors 10 ohm (at darlington's bases) are slowing this amp even further. My guess is they are not needed at all. Base resistors
are normally used if you want to slow down the OS. This OS is already slow enough 🙂
e) Seems like C11 (100pF) and CFB2 (12pF) values are too high, and also slowing down this amp.
I tried values 33pF and 5pF.
With all these small changes I got 12V/us slew rate, which is fine for small power amp.
The values of C11/CFB2 should be a result of the square wave simulation and stability (phase/gain margin) sims, and should be as small as possible,
while keeping amp stable (phase margin 50 or more), and square waves decent.
Not sure if you did open loop gain (stability) simulation; by looking at the schematic it looks it wasn't done.
Perhaps these values 33p and 5p could go even lower if phase margin allows for it.
f) simple amp like this, should be very stable, and should not need LR network at the output (for the sim).
The ideal is to sim without it, and make it stable and squares looking decent, and AFTER that add LR.
Good amp (unless it's very cutting edge) should work in the sim without LR.
If you can't make it stable in a sim without LR, it's a sign of future troubles in real build.
My sim attached, along with models.
Edit - I noticed another anomaly - your idle current control (adjusting RV1) doesn't work at all. As it is, with 82R, upper darlington has
366mA idle current, and lower one 6.5mA.
It's never gonna work like this. They have to more or less equal.
I suspect that you need to adjust R12/R13/RV1 to achieve symmetrical idle current.
This is also skewing all the simulated results, and might be the reason for the big output DC offset.
If you change R12/R13, it will affect VAS current, so you may need R21 adjustement as well. VAS current should be kept where it is now, 10-13mA.
So it looks like there is still a lot of work to make this amp working correctly.
Don't worry about the Thd values until these issues are addressed 🙂
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PS. I couldn't use original asc file from your sim, I was getting 'undefined symbols' errors.
Had to replace symbols for darlingtons, and add models for them. Not sure if this didn't mess up your original schematic, or sim results.
Also not sure if my Cordell_Models.lib is the same as yours, but I guess for such simple amp and common transistors it should not matter...
Note - it seems that value of R6 also affect symmetry of the idle current between upper/lower devices.
Values higher than 835 Ohm and lower than 1k makes this symmetry better, without changing R12/R13.
When idle current is more symmetrical, DC offset at the output also went down (e.g. with R6=1k, offset is 112mV).
Had to replace symbols for darlingtons, and add models for them. Not sure if this didn't mess up your original schematic, or sim results.
Also not sure if my Cordell_Models.lib is the same as yours, but I guess for such simple amp and common transistors it should not matter...
Note - it seems that value of R6 also affect symmetry of the idle current between upper/lower devices.
Values higher than 835 Ohm and lower than 1k makes this symmetry better, without changing R12/R13.
When idle current is more symmetrical, DC offset at the output also went down (e.g. with R6=1k, offset is 112mV).
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It seems like small changes in R6 are affecting symmetry of the idle current big time. And of course affecting current through Q2/Q3 (LTP), causing it be un-even. It seems like the current mirror in the LTP collectors is a way to go....
Well yes indeed, bring it up all the time with many amplifiers posted here.
Why I am so picky about DC offset in amplifiers.
Already been covered, you set DC offset with E96 or E192 series resistor aka 1% or .5%
As mentioned before with simplified amplifier 30mV to 45mV DC offset is usually tolerated by most.
So yes idle current of the output devices will not be equal. Normal stuff for any amplifier.
Why I dont tolerate more than 1 to 3mV DC offset, so output device DC bias current is also equal.
Regardless very simple to achieve with 1% or .5%
Sure I guess if you use a mirror it makes it easier. the proposed circuit didnt have a mirror.
So is simple to balance LTP with the one resistor that does balance it.
Why I am so picky about DC offset in amplifiers.
Already been covered, you set DC offset with E96 or E192 series resistor aka 1% or .5%
As mentioned before with simplified amplifier 30mV to 45mV DC offset is usually tolerated by most.
So yes idle current of the output devices will not be equal. Normal stuff for any amplifier.
Why I dont tolerate more than 1 to 3mV DC offset, so output device DC bias current is also equal.
Regardless very simple to achieve with 1% or .5%
Sure I guess if you use a mirror it makes it easier. the proposed circuit didnt have a mirror.
So is simple to balance LTP with the one resistor that does balance it.
Thank you for your effort minek.
To Post 81.
In my sim i did all set up with input shorted as written in Post 63.
I use E96 values as WD stated.
I had exactly that values. Then i start to sim sine and square wave.
I do not understand why you get this datas.
The Darlington symbol was from a hugh Upload from this Forum. If i remember right the folder is called zzz.
There i used a symbol which get no Error If i use BDW93C lib datas.
Kr Chris
To Post 81.
In my sim i did all set up with input shorted as written in Post 63.
I use E96 values as WD stated.
I had exactly that values. Then i start to sim sine and square wave.
I do not understand why you get this datas.
The Darlington symbol was from a hugh Upload from this Forum. If i remember right the folder is called zzz.
There i used a symbol which get no Error If i use BDW93C lib datas.
Kr Chris
Sounds like problems between Sim models or the model in general and what currents are thought to be
I dont deal with LtSpice issues
From the beginning of the thread I can only make judgement by posted data.
So far R3 with the LED current source has been 33r or 13r so that is well over 30ma to 55ma
If minek123 is reporting 600ma + of bias on one output transistor and the other only around 5ma
That indicates Massive DC offset and the Differential shown with 30ma to 55ma of current not 2ma
Would very much cause that problem. So I dont know the issue with the model or unable to help with Ltspice.
Dont know if the red led model has issues or what. I commented early on in the thread the Differential
is getting blasted with current. R3 would be around 330 to 470r with red led voltage drop.
Using a standard led model, I couldnt get 2ma without using a 2% or 1% resistor value.
I stick to zener circuit with defined zener model and can get currents with 10% resistor in sim.
As noted below me and stigigmla have both addressed the shown data. current would be very very high with shown R3 values.
Yes Thank you, as noted above the data I see posted in many schematics shows very high current with R3 value.
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For less confusion I show current data seen. Differential current is close to 55ma and bootstrap for second gain stage is approximately 10ma
My posted example circuit uses typical 2ma for differential and 8ma for 2nd gain stage/ Vas
This is not my proposed model or example, I simply replicate newest model shown, with transistor choices used and using LED for current source.
The LED as proposed is roughly set 2ma of current as expressed by OP with 8.2k which would be standard value. And needs 1% or 2% resistor to set current to 2ma with more expected 402r not 13r. Sorry I did not match your resistor ID numbers. Your boostrap current with 1k resistors would yield 10ma I set current to 8ma. My temperatures are set to 22c which is assumed die temperature in model. In real life thermal track transistor would follow the heatsink temp, and you have die temp in model, there is case temp, and insulator losses. To get any realistic bias settings in sim temperature would have to be much colder for thermal tracking transistor . obviously we set bias according to model, in real life is typical to use pot to adjust bias
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good morning WD
yes thre is a LTspice model or sim problem.
my valueas are now checked again and i get the values what you have. my R6 (your R3) is still 835R to get less DC offset.
LED
your R21 (my R3) is set to 402R and you get 2,1mA - if i do that i get 221µA - so i hav to set it to 13R to get 2,14mA.
?
yes thre is a LTspice model or sim problem.
my valueas are now checked again and i get the values what you have. my R6 (your R3) is still 835R to get less DC offset.
LED
your R21 (my R3) is set to 402R and you get 2,1mA - if i do that i get 221µA - so i hav to set it to 13R to get 2,14mA.
?
Hi minek
if i start your file with extention WD.org it is working
the other not!
so it is a sim -libary-symbol problem?
if i start your file with extention WD.org it is working
the other not!
so it is a sim -libary-symbol problem?
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1. There is something wrong with the current generator for the input. With proper components downloaded it should give very much too large current to the input pair. If it gives 2 mA there is something wrong in the simulation.
More often is the 2 transistor solution used and we begin with R6 = 2xR3 and then adjust one of them so we get near the same current in transistor 2 and 3. 330 and 680 ohms can be a begin.
2. The max rising slew rate from Q5 (VAS) is calculated from the formula I x t = U x C ( in Ampere, Farad, volt and seconds) where I is the current in R6+ Ib and C is the value of C5 + Ccb of the BD139. If I guess that Ccb at 20 volts is 17 pf it will be a total of 50 pf.
We use the formula as I/C = U/t and get 20v/us. The BDX transistors will maybe limit that a little bit but this is about the value we can expect. I couldnt find the value of Ccb for BD139 in the net so it is just a guess.
The sinking slew rate is calculated from max current in Q2 - the current in R5 + Ib. Should be 1 mA resulting in 20v/us.
3. If the DC voltage out is more than a few mv the current from the current generator is wrong.
More often is the 2 transistor solution used and we begin with R6 = 2xR3 and then adjust one of them so we get near the same current in transistor 2 and 3. 330 and 680 ohms can be a begin.
2. The max rising slew rate from Q5 (VAS) is calculated from the formula I x t = U x C ( in Ampere, Farad, volt and seconds) where I is the current in R6+ Ib and C is the value of C5 + Ccb of the BD139. If I guess that Ccb at 20 volts is 17 pf it will be a total of 50 pf.
We use the formula as I/C = U/t and get 20v/us. The BDX transistors will maybe limit that a little bit but this is about the value we can expect. I couldnt find the value of Ccb for BD139 in the net so it is just a guess.
The sinking slew rate is calculated from max current in Q2 - the current in R5 + Ib. Should be 1 mA resulting in 20v/us.
3. If the DC voltage out is more than a few mv the current from the current generator is wrong.
I didn't install or download any special symbols. The datlington symbols in my sim are standard symbols that come with lt spice.
It seems like your lt spice is different than mine....
So basically I can't run your sim, and you can't run mine 🙂
Can anybody confirm if you can run chermann's sim without any changes?
Can anybody confirm if you can run my sim (post #81) without any changes?
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Just posting this because someone highlighted this thread asking for help 🙂
If you want to provide a sim with unique models included like Darlington's then you need to provide them in a folder along with the model and symbol files so it is a 'click and run' sim.
If you open the examples files in LT and look at the PAsystem folder you will see the not just the sim file but all the model and symbols needed to make it a 'click and run' simulation.
So you need the .lib files and all the relevant Darlington symbol files in the same folder.
If you want to provide a sim with unique models included like Darlington's then you need to provide them in a folder along with the model and symbol files so it is a 'click and run' sim.
If you open the examples files in LT and look at the PAsystem folder you will see the not just the sim file but all the model and symbols needed to make it a 'click and run' simulation.
So you need the .lib files and all the relevant Darlington symbol files in the same folder.
thank you mooly for your quick response.
i will check maybe at the weekend..today not possible.
kr
chris
i will check maybe at the weekend..today not possible.
kr
chris
Mooly, I added standard darlington symbols that came with ltspice (Darlington folder) - e.g. SYMBOL Darlington\\xnpndrlngtn
and I included models for them from the 'current sim directory' (e.g. BDW93C.lib),
and it worked fine for me. The same concept as with any other symbol (e.g. for a regular npn transistor symbol) and model coming from .lib file.
So in my case symbol and model are not in the same folder (sim in post #81).
and I included models for them from the 'current sim directory' (e.g. BDW93C.lib),
and it worked fine for me. The same concept as with any other symbol (e.g. for a regular npn transistor symbol) and model coming from .lib file.
So in my case symbol and model are not in the same folder (sim in post #81).
I was just responding to a question I got asked about this thread as a general thing 🙂
Models are always an issue and so many sims as posted don't run for various of models and configured models and so on. Pots are another common issue in sims posted. Most folk want a sim that will just click and run with no alteration on their part.
Models are always an issue and so many sims as posted don't run for various of models and configured models and so on. Pots are another common issue in sims posted. Most folk want a sim that will just click and run with no alteration on their part.
Good evening
the LT spice file is working 👍 😉 👍
Yes the error was with the LED. i can swear i use a led but finaly it was just the symbol and the real type was a rect. diode. i realized it as i measure the voltage drop.
now i use a red led with 1,52Vf.
the darlington models have an error - i delete the X-NPN name and it works
i´ve got an error about the cordell LS844C (JFET) but dont know why...i delete it aut of the lib file...no error massage now.
DC values:
CCS is now at 2,1mA
R6 is as WD mentioned 759R - i get -22mV DC offset...in real life it has to be calibrated...
VAS get with the setup of both resistors R12,R13, --> 8,1mA
idle current of OPS is about 71,6mA and 76,8mA(NPN)
kr
chris
the LT spice file is working 👍 😉 👍
Yes the error was with the LED. i can swear i use a led but finaly it was just the symbol and the real type was a rect. diode. i realized it as i measure the voltage drop.
now i use a red led with 1,52Vf.
the darlington models have an error - i delete the X-NPN name and it works
i´ve got an error about the cordell LS844C (JFET) but dont know why...i delete it aut of the lib file...no error massage now.
DC values:
CCS is now at 2,1mA
R6 is as WD mentioned 759R - i get -22mV DC offset...in real life it has to be calibrated...
VAS get with the setup of both resistors R12,R13, --> 8,1mA
idle current of OPS is about 71,6mA and 76,8mA(NPN)
kr
chris
1khz square wave generator 1Vpp, 4R load, i do not shorten the caps (C1, C3) like minek...
i got 13,8V/µsec..looks good or?
i got 13,8V/µsec..looks good or?