@brian92fs Thank you, I only have the 4th edition and it does not include such text. We always need to know phase margin at the point where loopgain crosses 0dB and also gain margin at the point where phase crosses -180 degrees. I think that single number of loopgain at 20kHz is quite pointless.
I'm not sure I follow. If I look at the schematic in post #1 and the last schematic from lineup in post #297, they are very similar. The only material change is the addition of LTP degeneration and a different IPS and VAS CCS.
The changes to the CCS is the biggest change and in my opinion, a positive change.
The changes to the CCS is the biggest change and in my opinion, a positive change.
the schematic on the first message is no longer the original one, it is already a modified version following numerous comments and proposals.
I have the 5th edition, which states:
"
My practice is to quote the NFB factor at 20 kHz, as this can normally be assumed to be above the
dominant pole frequency, and so in the region where open-loop gain is set by only two or three
components. Normally the open-loop gain is falling at a constant 6 dB/octave at this frequency on
its way down to intersect the unity-loop-gain line and so its magnitude allows some judgment as
to Nyquist stability."
I don't think so. If I look at the next schematic Lineup posted in post #18, it's very similar to post #1. And in the posts before it, there aren't many recommendations on changes.
I expected that as well. In later versions of the book he might even differentiate between NFB re BJT and MOS output devices because the difference in distortion between them (when driven from low Z) can be more than compensated for (in favor of MOS) with higher Z-out VAS and CCS (cascode) - easily verified with sims as I did already.
the original circuit lacked rail decoupling and gate protection, gate resistors too low, etc etc....
several members have commented that the original circuit in post 1 should have not been replaced.
Self is written after that sentence as follows.
"The 30 dB figure assumes simple dominant-pole compensation with a 6 dB/octave roll-off for the open-loop-gain."
In other words, he was talking about 1-pole compensation.
This can also be interpreted as saying that ULGF is safe if it is 632kHz, and dangerous if it is 2MHz, but the reason he did not express this is because ULGF is already -12dB/oct or more due to the influence of the undesirable 2nd, 3rd, etc. poles, he expressed a loop gain of 20kHz
By the way, your loop gain measurement connected R12 to the NFB network side. TMC interpret as local feedback from OPS to second stage (VAS) and global feedback nested it.
When measuring global feedback, connect R12 to the output side. You should get a loop gain characteristic similar to one-pole compensation.
There are just a few more optimization steps to do to help Lineup finish this design before we look for PCB design volunteers 
If you can do an AC analysis to check the amplifier frequency response in your simulator, you can do a loop gain analysis (LGA). This is how to do it:-
1. Save your existing circuit under a new name eg Cello_LGA
2. Remove the AC stimulus at the input of the amp and short the amplifier input to ground
3. Where the feedback resistor connects to the amplifier output, break it and connect the AC source between the feedback resistor where you disconnected it and the output.
4. Label the node going to the feedback resistor (or if your sim s/ware does that automatically, note down the node name). For our example in LTspice, I've called this node x
5. Make sure ALL feedback paths incl any TMC, Miller comp caps or phase lead caps across the feedvback resistor are on the feedback resistor connection to the AC source and do not bypass it and go to the output side
6. Set the AC source stimulus to 1
7. Run the AC analysis
8. In the output window, plot the quantity V(vo)/V(vx) (follow the waveform math conventions for your simulator)
You should get a plot that looks like this, which is a loop gain plot (this example is a TMC amp). This will allow you to directly assess the loop gain stability of any amplifier and optimise the compensation design for best overall performance
For reference, here is the circuit I used to make the above LGA plot, so you can see how the AC source is arranged:-
If you can do an AC analysis to check the amplifier frequency response in your simulator, you can do a loop gain analysis (LGA). This is how to do it:-
1. Save your existing circuit under a new name eg Cello_LGA
2. Remove the AC stimulus at the input of the amp and short the amplifier input to ground
3. Where the feedback resistor connects to the amplifier output, break it and connect the AC source between the feedback resistor where you disconnected it and the output.
4. Label the node going to the feedback resistor (or if your sim s/ware does that automatically, note down the node name). For our example in LTspice, I've called this node x
5. Make sure ALL feedback paths incl any TMC, Miller comp caps or phase lead caps across the feedvback resistor are on the feedback resistor connection to the AC source and do not bypass it and go to the output side
6. Set the AC source stimulus to 1
7. Run the AC analysis
8. In the output window, plot the quantity V(vo)/V(vx) (follow the waveform math conventions for your simulator)
You should get a plot that looks like this, which is a loop gain plot (this example is a TMC amp). This will allow you to directly assess the loop gain stability of any amplifier and optimise the compensation design for best overall performance
For reference, here is the circuit I used to make the above LGA plot, so you can see how the AC source is arranged:-
Looking at the output mosfet being driven directly off the VAS, I do not think that should be a major issue here - I've seen that done on a lot of mosfet amplifiers. It might however be an idea to decouple the bias setting resistor with a 1-10 uF capacitor since the device input capacitance is not linear.
If referring to amplifiers that are Miller compensated - so have a single dominant pole at just a few 10's of Hz - then the only way to get 40 dB loop gain at 20 kHz is to make sure you have enough LF gain to do this ie you have to raise the open loop gain, BUT, it also means when you close the loop the unity loop gain frequency (ULGF) will go UP. The risk of that is you are then flying very close to the output stage HF pole which comes with additional phase shift and may make the loop unstable. The other risk is that you trigger HF instability in the OPS - this is a separate mechanism from loop gain stability. So, in general, for Miller compensated amplifiers, the useful loop gain at 20 kHz is around 30-35 dB. This is what Self is saying in his statement.
TMC/TPC do not suffer this issue because you do not have to increase the loop gain at LF to raise the loop gain at HF - which is what you must do with Millier aka dominant pole compensation. With TMC/TPC, you simply shape the loop gain response using the appropriate RC network(s) to cause it to drop off at 40 dB/decade but then revert back to 20 dB/decade before the amplifier ULGF. Both of these techniques have come into vogue over the last 10 years or so (although Self mentions TPC in his 1996 edition) because they were popularized by Cordell and Edmond Stuart - and specifically TMC because it does not suffer from closed-loop peaking which TPC does.
For modern sustained beta bipolar devices, a good rule of thumb for the ULGF is:-
EF (ie single follower device output) ULGF = 3 MHz
EF2 = 2 MHz
EF3 = 1.5-2 MHz (with additional steps to prevent parasitic instability - see for example Wolverine Amp)
Although mosfets in general have higher fTs, once you get beyond 3MHz, the layout becomes very important, so you really have to think about that. So for mosfet OPS, the recommendation is 3 MHz
(BTW I am not an expert, just a committed amp builder
)
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