Ok, I was avoiding to post the whole thing for clarity... It seems we must.
Here the explanatory notes:
Here Q469 (74HC673) and Q470 (74HC674) form a 16 Bit Memory buffer 1 Bit wide. Another set of words to describe this circuit is "FIFO".
Serial Data from the Yamaha SPDIF Decoder enters Q469 - which performs serial to parallel conversion. It is functionally the same as 2 X 74HC595 cascaded for 16 bit.
The clock to load bits is the bitclock from the Receiver (Q401).
The "Mode" line controls the output storage register which holds 16 Bit worth of data and is controlled by a one shot pulse generator on each WCK edge. On the rising edge of this pulse the 16 Bit in the serial to parallel register are loaded into the output register.
All 16 Bit are connected to Q470 which is a 16 Bit parallel in, serial out shift register. After Mode is high (valid data is present at the outputs of Q469) the first falling clock edge performs the parallel load. With Mode low the falling clock edge clocks out the bits on pin 6 as serial data, delayed by 16 BCK periods and with the ability to use a clock asynchronous with the receiver BCK to clock out the bits from Q470 and into the SAA7220 Filter, together with a bit clock derived from the secondary PLL Clock around Q457 (J-Fet & LC Colpits oscillator).
The clock pin is driven by an AND gate that performs AND on the Receiver BCK and on the secondary PLL Clock. With either clock low after both clocks were high generates an edge. I think this uses the Receiver BCK to open a "time window" for the secondary PLL clock to create the actual edge. There are many extra dividers, flipflops, one shot pulse generators etc...
A lot of this could be simplified without any functional penalty.
For starters Q469 & Q470 could be replaced with a 74HC40105 FIFO which could be used to handle both WCK and DATA storage. Then Receiver BCK and DAC BCK can be fully decoupled. As WCK is sampled with DATA we get everything in sync at the output, so a lot of extra logic to align stuff no longer is needed.
The Preamble detector on the other hand is genius. Easy to replicate we could use VCXO at the relevant clocks.
Or we can take a WM8804/8805 which in effect has all this build in with a DPLL with usually sub 50pS P-P (not RMS) jitter replacing the VCXO or looking back to DA-12 the VCLCO.
Now, do you still want to argue with me that Q469 & Q470 do not constitute a 1bit wide, 16 bit deep FIFO (e.g. 1/4 or 74HC40105)? If so what do they do in your considered opinion?
Thor
PS, I have somewhere a service manual with addendums for a modified version of this that uses optoisolation on the 16 Bit parallel bus and pulse transformers for clocks. I looked but cannot locate it. I actually encountered this unit in reality. It was a pro-audio version of something related to Philips LHH-1000. The manual may actually have been a xerox and I never scanned it.
It all revolves around the '673 and how it operates. Below is what we are given.
Q469 /CS and R/W are tied to ground and /STRCLR is tied to +5V. The only control pin with a changeable state is MODE or to give it it's alternate name /STRCLK.
According to the table above there are only two possible states of operation given that /CS and R/W are always low and /STRCLR is always high.
At the start of a L/R frame, when it is high, WC is low forcing SHCLK to remain high so nothing is clocked in. When WC goes high, coincident with the start of data, the left channel 16 bit data is clocked into the shift register and when WC goes low again after the sixteenth bit is loaded the clock stops. As well as stopping the clock WC also triggers Q471/2 delivering a pulse to /STRCLK loading the 16 bit left channel data, in parallel, from the shift register into the 16 bit wide and 16 bit deep storage register. The same process in then repeated for the right channel. In short, at the falling edge of WC the parallel word moves across by one.
The 16 bit serial in parallel out (from the perspective external to the chip) shift register and the 16 x 16 storage register are two distinct but connected entities. You cannot load the storage register without first loading the shift register. You cannot treat it as a 16 x 1 because there is no serial output in the operating modes chosen and in the modes where there is a serial output you read back over the same pin you wrote in with.
ABSOLUTELY NOT.
It all revolves around the '673 AND '674 and how they operate TOGETHER.
HERE is what we are given (for clarity):
Q469 (673) AND Q470 (674) are combined as a serial in, serial out 16 Bit Memory where the first bit in is also the first bit out, so combined they behave as FIFO.
I did not suggest that 74HC673 = FIFO.
But that 74HS673 + 74HC674 AS CONNECTED HERE function as FIFO, with Q469 Pin 6 Serial Data In, Q469 Pin 2 as Input Bitclock, Q469/470 Pin 5 as flow control and Q474 Pin 6 Serial Data Out, Q470 Pin 2 as Output Bitclock.
Do you still insist that this is not the case?
That is do you insist the circuit consisting of Q469 & Q470 does not have a serial data input and a serial data output and no other Data In/Out only Bit Clocks and flow control, with the first bit in also the first bit out (First In First Out = FIFO)?
Thor
This is kind of an Elastic Buffer, in a modified form. The conventional FIFO uses the same clock for data in and data out.
Aka "asynchronous FIFO" as exemplified by the 74HC40105.
Not necessarily. Here the 74HC40105 FIFO IC:
DIR = Data In Ready (Flag)
SI = Shift In (Clock Rising Edge)
DOR = Data Out Ready (Flag)
/SO = Shift Out (Clock Falling Edge)
In principle we can link SI & /SO together and clock out one bit as we clock in another.
But this is no requirement.
The requirement is to ensure the FIFO has data in it when we attempt to clock it out.
So we can use the FIFO as elastic buffer.
For example to go from a BCK/WCK/BBCK IIS Input with BCK = 64 X WCK to the TDA1541(A) simultaneous format with LE, DATAL & DATAR.
We connect two 74HC40105 is cascade, for 32 Bit. After the first FIFO is filled we start the output clock. We constantly clock out 16 Bit per WCK. On the input side, we clock in 16 Bit's out 64 using the 64 X WCK Clock with stopped clock to mask off unwanted bits. The "elastic buffer" soaks up the speed difference.
Thor
I asked a simple yes/no question from on a technical question.
There is no room for opinion, nor for leaving anything.
Either it is true that the circuit discussed behaves the way I describe, or it is not true.
If it is not true, please point out my error.
I am here to learn and stand to be corrected where my understanding is wanting.
After that we can discuss why replacing the two IC's in the sample Circuit with a single FIFO IC would (or would not) work.
Thor
But the goalposts have moved from here
To here
Those are two very different questions. The first assertion is just plain wrong and the second misrepresents what I wrote.
Have they? In the circuit discussed, we have, for the system formed out of the two IC's a system (let's blackbox it) with a serial data input and a serial input clock input, a series data output and a serial output clock, where data enters with MSB of a 16 bit word and exits with the MSB first.
I will assert that this describes EXACTLY the function of the series of 74HC673 & 74HC674 as used in the DA-12 Jitter killer.
It also accurately describes a FIFO Memory block (be it discrete transistors or a FPGA construct).
You wrote nothing explanatory, just "I disagree".
I cannot misrepresent that, as you refuse to state what specifically you disagree.
If you disagree that the circuit works the way I describe, please describe how it really works.
In order to "disagree" that it functionally forms a FIFO memory Block that could be replaced, in principle, by any other suitable FIFO Memory block you need to show that my analysis of the original circuit is wrong and it therefore is not functionally a 16 Bit FIFO Memory Block. Then you need to clarify what it actually is.
So, please, where is my explanation of the function of the 74HC673 cascaded with 74HC674 Circuit wrong? Then we can clarify why what I (and the Marantz Service Manual) claim as function is not the actual function, what the ACTUAL function is and then understand the circuit.
Thor
I thought it was pretty clear but here goes. Your contention that the '673/'674 combination form , in your words, a 1bit wide, 16 bit deep FIFO (e.g. 1/4 or 74HC40105.
Especially the 74HC40105 bit.
I didn't replace lm317 yet, without C28 it doesn't oscillate. I will keep the thread posted
Ok. So what is it then?
Are the data in and out are not serially (the parallel connection is only between the two sift registers)?
Is the stored data not 16 Bit?
In terms of order of data, the first bit in will be the first bit out?
I actually posted it EXPLICITLY as an illustration of an overcomplicated way of making a FIFO.
If you insist it doesn't form a FIFO memory, what is it?
And don't try to fob me off with "just read the datasheet". I have. Before I ever posted about it.
And that was the point of the post. And yes, you can. Obviously not as a pin-to-pin substitution, but as a functional block.
Thor
Which brings us right back to
As far as I am concerned there really is nothing more to be said. If you can turn a '40105 into a '673/'674 combo fair play to you.
You are looking at the specific circuit and you do not see the function.
DA-12 you see a serial to parallel converter that then dumps the parallel data into a parallel to serial converter.
You ask "Where is that in the 40105?". It's not there.
I look at it this way:
Either circuit has serial in and out.
Each with its own clock.
Each circuit stores 16 Bit.
Each circuit operates on a first in, first out basis.
I am utterly uninterested in the process that leads to this result. Just the result
In that case 1/4 of a 40105 does EXCATLY what the 673+674 circuit does.
It needs a slightly different setup of the flow control, but in the it's 16 bit in, 16 bit stored, 16 bit out.
Is that really so hard to grasp? Two very different circuits, but an identical result.
Thor
You're a funny guy Mr T. I have to congratulate you in the way you have neatly segued past the actual bone of contention.
Ok, let's use your own drawing as basis:
1) Do you agree that the left side is redrawn from your diagram and accurately represents the combination of 673 & 674?
2) Do you agree, that functionally, having only serial in, serial out plus clocks and flow control which are not shown (and yes, flow control will be different) the structure on the left performs as far as the serial data stream on in and out is concerned ABSOLUTELY IDENTICAL to 1/4 (one chain) of the structure on the right.
That is:
1) if we put the left and right structures into a box, each with it's own flow control
2) if we apply the same input data and input clock to both boxes
3) if we apply the same output clock to both boxes and observe the output data
4) we do observe on both boxes data output the exactly same data, syncronised with the output clock?
My contention is that if 1) - 3) are true then 4) is also true. And 4 can either be true or not.
And that is the bone of contention.
If you content that 4) is not true, please elaborate why.
I content it is true, because:
a) after the full 16 Bit are loaded into the 673 shift register MSB first, they are immediately transferred to the output register and then to the 674 shift register and the next high to low transition of the output clock will present the MSB on the output and then the subsequent Bits on each transition.
b) after the full 16 Bit are loaded into one if 4 strands of the 40105 FIFO the next high to low transition of the output clock will present the MSB on the output and then the subsequent Bits on each transition.
Thus, I further content that:
c) the output data is identical from either circuit, disregarding the specifics of each circuits internal function
d) the two circuits are functionally equivalent and may be substituted (with the necessary adaptations of flow control) for each other.
QUOD ERAT DEMONSTRANDVM
Thor
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"You're traveling through another dimension -- a dimension not only of sight and sound but of mind. A journey into a wondrous land whose boundaries are that of imagination. That's the signpost up ahead -- your next stop, the Twilight Zone!"
Hi all, let me explain: rfbrw does this not the first time. Rfbrw says "you are wrong", suggests "read the ds", without explaining what actually is wrong, just goes on to insists that it's wrong, leading to long and unnecessary discussions. I know that from my own experience.