A little Mclk board aside is also feasible as in this week pcb iteration I have putted a SMA + UF-L connector at the base of the BC327. Close to it There is a SMA + UF-L for the Bck_FDEM.
W/O theMclk circuit you showed and plan to try for real ("the sim behavior of clock noy good enough" dixit) , the PCB is for the moment 150 mm x 76 mm.
The problem remains the sim mode. The chineese board seems NLA on the site of the designer. Or maybe you have a link at ALixpress ?
2 or 3 solutions I see : putting header on board for such a board with eventually no SMA for BcK_FDEM but a link direct to the I2S input of the board via the header..
JLS USB to SIM : expensive (75 euros W/O VAT+ 20 euros shippment ; 120 euros for the whole for Europe ) : Mclk can be injected through pin header ! But it s 45/48 K hz SDKA crystals (not what is expected here.)
ECEDESIGN SIM hardware embeded or aside but made more "discrete" and better power/decoupling arrengment + linking between flip flops that what already exists here.
And of course any third party cpld with input and output as the one you showed and cheap and good enough.
W/O theMclk circuit you showed and plan to try for real ("the sim behavior of clock noy good enough" dixit) , the PCB is for the moment 150 mm x 76 mm.
The problem remains the sim mode. The chineese board seems NLA on the site of the designer. Or maybe you have a link at ALixpress ?
2 or 3 solutions I see : putting header on board for such a board with eventually no SMA for BcK_FDEM but a link direct to the I2S input of the board via the header..
JLS USB to SIM : expensive (75 euros W/O VAT+ 20 euros shippment ; 120 euros for the whole for Europe ) : Mclk can be injected through pin header ! But it s 45/48 K hz SDKA crystals (not what is expected here.)
ECEDESIGN SIM hardware embeded or aside but made more "discrete" and better power/decoupling arrengment + linking between flip flops that what already exists here.
And of course any third party cpld with input and output as the one you showed and cheap and good enough.
You haven't seen what was made here in that regard , how do you know it could be made better ??
if you do it as per John schematics , in an 4 layers board respecting the digital laws , it works perfectly , and it should be as close as possible to the TDA , not at all in a remote board
if you guy's want to make it "ultimate" , the cheapo way is the wrong way .........
.
https://www.aliexpress.com/w/wholesale-SAA7220-TDA1540-TDA1541-driver.html
Ok, for the single TDA1541, what do we loose if we use IIS over SIM?
The ability to run faster than 192kHz (16 Bit IIS) or 96kHz (24/32 Bit IIS).
Non of which I will loose a lot of sleep over.
TBH, 176.4/192k would be nice, I have a lot of SACD material transcoded to 16/176.4 using Saracon.
I think it would be this if we really need to.
We have this schematic from John (link to post with original):
Not sure if there was a later bug fix.
I would replace U1/2, U3/4 & U5/6 with 1.8V, 16 Bit logic, e.g. Texas Instruments SN74AUCH16374DGVR or similar LCX/LVC logic.
Probably use a set of NC7SZ74 or similar flip-flops or use another 16374 as U7/8/9 (bank 1 with spares) and as reclocker from MCK (bank 2) just to get better efficiency and layout. One would need to look for generic parts at LCSC/JLCPCB.
If we go 1.8V all the way, attenuation becomes unnecessary and a single resistor in series with the TDA1541 inputs will do.
Honestly, if we ditch the completely unnecessary "quiet time" we can simplify the circuit a lot. The upper section is in effect a 33 bit Shift register (1 Bit for the 1 Bit IIS offset). U14A & U14B act as "gating" muting all bit's outside the 16 Bit window generated by U5/6/8/9 and U14D "gates" the Bit clock.
I think a set of 4pcs 74AUC16374 can replace all flip flops. One 74XXX04 can provide us with the needed inverters. Either some 74XXX08 or we just use XXX74 Flip flops with the correct combination of the preset pins, or we use a 16374 with OE (and external Pull-Up's).
Anyway, I'll spend time on this to rationalise and simplify, should there be a real need.
I dislike this scheme, as it keeps the bitclock running at the original IIS rate. So faster than 96k is nominally out. Might still work, but if it does, so will IIS. If BCK o TDA1541 works at 12.228MHz (which reportedly it does) then we can do 192k/IIS without issues. So honestly, I see no benefit to using this over IIS.
Ideally we find a fast FIFO with enough bit's etc., so we clock in at IIS BCK with stopped clock when there is no data and clock out with IIS-BCK / 4 (3). I think these days we would use a CPLD, if anyone is up to speed with low cost, widely available options, and to program them for what I propose (FIFO with 32Bit IIS input and 16 Bit SIM output ad IIS BCK / 4) do cut in.
Thor
No , because there are no bugs to fix , you may not like it but the stop clock is the way to go and at 2.5 v no needs too of any attenuation , even if i will try some ( voltage and rise time ) to see if it make any sens or not
and remenber , John schematics and ideas works great in the real world , what about yours , we now know that -15 v ref was a deep fail , what about all the rest ?
.
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I reference all sorts of writ. Holy, Unholy, the bard. All is grist for my mill.
Where I am is Sub Rosea Sub Crucis.
The name Diablo was not from me.
The AMR DAC - if you see the shape you will know why:
Technically it should have been Kode 0, not Diablo.
The "iFi Diablo" was codenamed "red label" (to go with the black label) and was inspired by
I would have liked to have gotten out a new series that would have refreshed the whole range and kept the Whiskey allusions with the "red label" the base model (with a gradient
Normally my own "working titles" come from experimental aerospace.
The original ifi iDSD micro was actually "X-2" and the "xDSD" started life as "X-15 Hyoersonic".
I think I'll let you ask @abraxalito.
More generically on filters (focusing on digital filters, but applicable more general), I wrote a little white paper that starts:
ALL DIGITAL FILTERS FOR AUDIO ARE WRONG.
ALL OF THEM, INCLUDING THE 'NO FILTER' OPTION.
THIS IS WHY WE NEED YET ANOTHER FILTER!
https://ifi-audio.com/wp-content/uploads/2019/04/iFi-audio-Tech-Note-The-GTO-Filter.pdf
The whole thing was more technical, coherent and to the point before S&M got hold of it and "made it readable". They also insisted it had to be the GTO filter and not TO. So Mr Gibbs somehow got dragged in kicking and screaming and resisting until tasered and tranquilised, though he was wholly innocent.
I actually called the filter discussed the "Transient Optimised Filter" in counter to the "Transient Aligned Filter". It is a 32 Tap (at 44.1kHz) asymmetric FIR without pre-ringing and just enough roll-off to be effective as a filter. It's very much in the tradition of the Pioneer Legato Link and Ayre MP filter. Transient Aligned is a symmetric FIR filter of at least 16k taps length.
I think a crucial part in the paper is:
"Wherever there is a difference, there is also a preference.
Subjective listening preference may be informed by a range of factors including a learned or acquired response to recorded sound (e.g. what sounds ‘right’ or ‘hifi’ is not what sounds natural in comparison to a live performance), including direct referencing acoustic music performances."
Anyway, I decided to look into what, how and why we "hear" filter differences and what it might take to make a filter that combines the benefit of a digital filter (e.g. zero cost, perfect repeatability, zero tolerance) with something that would more or less resemble the results of Non-Os with SINC compensation, with better rejection of post Fs digital images.
One critical point to consider is that the human hearing has shown to have a location accuracy of transients equal to around 5uS time domain resolution. Now a 5uS cycle is 200,000kHz. No, I'm not suggesting "we can hear 200kHz", but rather that human hearing is highly "unlinear".
Thus working on a linear model, as we generally do in audio electronics and without properly referencing the actual "unlinear" model of hearing to the best knowledge available will cause misleading conclusions on how to achieve "minimum audible fidelity impairment" and possibly even (I know this is questionable and will court controversy) "maximum audible fidelity enhancement".
I know, it's not actually what you asked, but it is the missing centrepiece of the puzzle, without which other bits and pieces that fit somewhere in this (remember "Wherever there is a difference, there is also a preference.") do not seem to fit the puzzle or make sense.
93 93/93
Thor
Ask to the aeromodelism french that fligths at the level of english grass (aka lawnmower QI), a troll or gobelin DAC, he knows better than everyone here. You can be sure the fiter will work, i.e. what that enters is not what is outputing... as the digesting. Too bad that the ignore function doesn't work when reading this thread when non logged (coockies ?)
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That's the HDAM Jfet gate input with serie low pass . Chips were Taiwann S1 or S2 iirc ! Those chips sounds totally different tonally than the older european made that are darker and less ultimatly detailled.
Strangly having both a Taiwan 1998 as an european SI, all the TDA1541A dacs or cd player I made and tweakes, all asked different setups to acheive a good tonal accuracy.
So there is a passive low pass + psot filter after... if I read it well enough ?
Strangly having both a Taiwan 1998 as an european SI, all the TDA1541A dacs or cd player I made and tweakes, all asked different setups to acheive a good tonal accuracy.
So there is a passive low pass + psot filter after... if I read it well enough ?
For now the 4 layers single TDA core PCB is ok to test if no further evo to simultaneous mode embeded and/or embed balanced MCLK.
I had to give up dip14 packages but a pcb can be easily made as I have backups....
There is an internal trace with jumper on top than allows or not the I2S Bck FDEM feeding for active sync. I have to add a jumper to pin 26 to 28 prg mode but that's a final detail .
So SMA+UF-L input : pin 1 to 4 , MCLK (BJT attenuator buffer option) + BCK FDEM active sync : internal or external options (jumper of SMA/UF-L). for sim mode or delayed MCLK (think Mori Clock no probs of long sma cables here for the ones who know what I mean) or very short uf-l cable 1" if MCLK classic pcb aside (@Markw4 , etc : ask about stop clock options of your front ends to feed theboard as per discussed in the thread)
I dunno if there can be some interrest for more than myself and the few I planned to send to be testes by T, Z, or A. fellows if they want to help too to their own measurement or to check the pcb quietness), but anyway it takes care of details with great helps during the dev process.
Of course it can evolve.
I had to give up dip14 packages but a pcb can be easily made as I have backups....
There is an internal trace with jumper on top than allows or not the I2S Bck FDEM feeding for active sync. I have to add a jumper to pin 26 to 28 prg mode but that's a final detail .
So SMA+UF-L input : pin 1 to 4 , MCLK (BJT attenuator buffer option) + BCK FDEM active sync : internal or external options (jumper of SMA/UF-L). for sim mode or delayed MCLK (think Mori Clock no probs of long sma cables here for the ones who know what I mean) or very short uf-l cable 1" if MCLK classic pcb aside (@Markw4 , etc : ask about stop clock options of your front ends to feed theboard as per discussed in the thread)
I dunno if there can be some interrest for more than myself and the few I planned to send to be testes by T, Z, or A. fellows if they want to help too to their own measurement or to check the pcb quietness), but anyway it takes care of details with great helps during the dev process.
Of course it can evolve.
Attachments
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Hummmm, post number 999(0) above the reverse of 666(0) .... we swimm in a Crowley's nightmare.... ahaha (not funny, is it ?)
Insurection mini Diablo PCB (you buy the wheels !)
With all my 42 number sympathy.
Insurection mini Diablo PCB (you buy the wheels !)
With all my 42 number sympathy.
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yes
and not an reactive elements too.
.
Maybe the best way will be some current buffer with low impedance output.
And then IV circuit?
BTW someone post formula or link, about digital images in function of Fs?
I am not in the mood to dig in... 🤔
I am not in the mood to dig in... 🤔
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I heard it. Bit Meh. Probably an upgraded Grundig CD9009 might do better.
No. Each Output has a standard active feedback I/U conversion and separate 2nd order Sallen Key lowpass, just using discrete Op-Amp's. Even back in the 90's I found the HDAM circuit questionable and usually bypassed them when modding players (CD-63/67SE) that had "HDAM" buffers after the Op-Amp's. OPA165X/167X (same chip really) or OPA1656 will be better to my ears.
Thor
Formula? It's in the picture...
But real DAC's do not follow the theoretical SINC response.
If you want something simple, this page:
https://web.archive.org/web/20240223040226/http://www.atx7006.com/articles/dac_frequency_response
Scroll to the bottom:
I normally find that shooting for +0.1dB over theory @ Fs/4 works for me, so +1dB @ Fs/4 and +0.2dB @ Fs/8.
Thor
Looking good, but being german, so much unrequired asymmetry.
Also, the Os-Con's look small (physically) and the 100uF AC feedback capacitors in the TL431 voltage divider look huge.
Thor
No it is not... Just marked red lines in relation to n x Fs. But without frequency?
Maybe it is more informative, it is stated for 1 x Fs that images are 11/12 Fs and 13/12 Fs arounf Fs point.
But
It is not stated for 2 x Fs, 3 x Fs and so...
Since the F axis is linear, and distances from 1 x Fs images are the same as 2 x Fs marked images, probaly
should be the same?
.
n = 1
(11 / 12) x n x 44.1KHz = 0.9167 x 44.1KHz = 40.425 KHz
(13 / 12) x n x 44.1KHz = 1.0.83 x 44.1KHz = 47.775 KHz
.
n = 2
(11 / 12) x n x 44.1KHz = 0.9167 x 88.2KHz = 80.85 KHz
(13 / 12) x n x 44.1KHz = 1.0.83 x 88.2KHz = 95.55 KHz
....
Anyway, NOTE that it is for Sine wave period = 12T.
.
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This subject for sure generates some musings...
Very interesting. Several approaches here to avoid pulse ringing, interpolation issues etc. After several readings about the subject, I believe the PC-based proponents (besides choosing custom designed software filters) also can use filters like the PGGB-RT: it have milions of taps, so in theory, although the ringing can be longer (and being contrary to solutions like the iFi), the "garbage" (ripple in the response and pre/post echo) is buried below 32bits level, if I understood well, and DAC will not reproduce it. Some people indeed liked it. But I'm not fully sure if the pulse ringing also vanishes in level. This and any custom software filter can be tested in real time with player like Foobar, so it really have some proponents. But then, we can condenmed to use only PC and not another sources.
Maybe is a perfect time to test the impulse response and square wave for the PGGB-RT I'm using, but then I need a recording having that... too busy for chasing one... the ARTA can generate pcm files from it's generator, but the square wave one is unstable...
A lot of things to test, for people using DAC's like this with PC.
Even with every gun we use to shoot this problem, it will not eliminate the source problem: in fact, ADC also (obviously) works as a sample-and-hold manner, for PCM recordings, and "freezes" for several µs until next sample is requisited, so at this moment, it register the input. Much like displays works these days: LCD, OLED etc are sample-and-hold based, with consequences for the eye visual motion detection (is interesting to compare with a impulse dusplay, like CRT: I do). Several contermeasures can be taken to mitigate (backlight blinking etc). Even with differences for visual vs acoustic workings, one is tempted to think if the S/H behaviour is the main "digital issue", especially after papers like of these from the iFi (instantaneous time detection of the ear), and the better sound for true high sampled recordings. So, in this view, especially the 44100/16bits will have conceptually audio smearing.
Very interesting. Several approaches here to avoid pulse ringing, interpolation issues etc. After several readings about the subject, I believe the PC-based proponents (besides choosing custom designed software filters) also can use filters like the PGGB-RT: it have milions of taps, so in theory, although the ringing can be longer (and being contrary to solutions like the iFi), the "garbage" (ripple in the response and pre/post echo) is buried below 32bits level, if I understood well, and DAC will not reproduce it. Some people indeed liked it. But I'm not fully sure if the pulse ringing also vanishes in level. This and any custom software filter can be tested in real time with player like Foobar, so it really have some proponents. But then, we can condenmed to use only PC and not another sources.
Maybe is a perfect time to test the impulse response and square wave for the PGGB-RT I'm using, but then I need a recording having that... too busy for chasing one... the ARTA can generate pcm files from it's generator, but the square wave one is unstable...
A lot of things to test, for people using DAC's like this with PC.
Even with every gun we use to shoot this problem, it will not eliminate the source problem: in fact, ADC also (obviously) works as a sample-and-hold manner, for PCM recordings, and "freezes" for several µs until next sample is requisited, so at this moment, it register the input. Much like displays works these days: LCD, OLED etc are sample-and-hold based, with consequences for the eye visual motion detection (is interesting to compare with a impulse dusplay, like CRT: I do). Several contermeasures can be taken to mitigate (backlight blinking etc). Even with differences for visual vs acoustic workings, one is tempted to think if the S/H behaviour is the main "digital issue", especially after papers like of these from the iFi (instantaneous time detection of the ear), and the better sound for true high sampled recordings. So, in this view, especially the 44100/16bits will have conceptually audio smearing.
Many thanks for the feedback (and PM advices also : much appreciated).
I checked through hole Sanyo Os Con catalog and don't find 1200 uF/16V. My prefered are the SEP serie that has not such high capacitance. When I look at SEPC/F the max is 1000 uF and are 10 mm diameter as the footprints I chose (with a margin to 12 mm diameter spacing on the pcb and double spacing gap for the TPH in order some diyers can choose their own. I disllike a lot the SEPC/F I plenty have but found they sound zingy when used in an anlog DAC supply (pin 15, or else PCM dac ics I tried : AD1862, etc)
So, beyond the excellent ESR of the OSC CON, I find the new ones not sounding as good as the NLA formers and for my tastes till now, mostly for the -15V (so here I put a margin for bigger caps and double leads pitch gap : 5mm + 7mm). Of course, on must hear your design with the BOM as it was simed like that and the tricks you use are subtles and based too on listening long experience (that matterd a lot in my agenda : I bougth the first microIdsd from Ifi but couldn't affoard CD77 from AMR). ANyway I found the SEP serie the best of all the new oscons ! Because darker and less zingy (barely soft at the opposit of the SEPC/F) if not at all, but I don't like polymer in analog decoupling but another brand model (I literraly tried all the new polymers models and brans for my former TDA DAC Audial core based and the winner wasnot an os-con : whatever they have same esr & inductance at iso capacitance/voltage : the do NOT sounds the same too me, whatever I repeat the tests. BUT and it is a huge one, it was not tested in a shunt PS !
What the assymetry you are talking about please ? SMA pads ? Tracks on top layer ? Else ? : power side ( the many island on insides layers make it the topsymetry for eyes difficult but I can try better)?
For the tracks, the minimum spacing I use is the text book x3 width spacing (used for flip flops vinicity for illlustration). On the longer tracks FDEM, AoL/R, assymetry was a question of spacing with some signal vias, or to break too long // Tracks for antena coupling despite the spacing here is huge already (no needs of via fencing walls for instance). Sometimes I used assymetry to avoid things like M4 through hole in a corner (WRclk uf-l) or to make shorter the tracks for Mclk and FEDEM_Bck : but that's my french Cartesian side 😉 : in practice it certainly is not mandatory, so I can align (I do like too it looks good 🙂 )
As I send you a pcb, I'd like you find it looking good too 😊 !
Edit : I'm planning something in order you use the Super caps option you prefer. I willl use this pcb above cause the super caps are a little expensive for my own needs).
The TL431 caps are 10 mm diameter foot print, so caps could breath with all the close heat : double space leads gap here : 5mm and 2.5 mm 😉
(here btw my experience is the Pani FR are f....g good but according the smoothing caps chosen before; Pan FM here, nope; Pan FC yes or not (they are very clear and neutral : my ref to swap a sepc/f on analog sides)
What is the spacing of the Super caps you use, please in order I check the footprints needed.
cheers
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Or simply just an I/V with very low impedance input BJT (output impedance TDA 1541A that high ???) as the discussed shematic has a lot of pins filtering ? Jfet seems out cause unconcistancy (T.'s input sooner inthe thread)
By the way I wonder if the outputs of the TDA1541A are not internaly protected by diodes or somewhat ? I know AD1862 hasn't, @Alexandre reported about that last chip times ago.