@tonimxp ,
I didn't understand it the first time, so I asked maybe three times myself : I requote :
"You MUST use IIS BCK to divide down, not SIM BCK"
If you wait a little there should be a pcb from me or others with 4 layers according Thorsten's roadmap.
For your 2 layers question, there is a guy which have 20 years of experience and use it with hybrid starground and islands : Pedja Rogic. That's my today's reference at home aya2 2014 (modded front end with high end clocks and some trickies caps modes known as Eldam modes in Aya2/4 manual and some others writed nowhere). There is a GB for 45 euros the unpopulated board on his site (Aya5) with toshiba's dicrete I/V diamond like. Till now better than all you can find here. We have good expectations for the one to come here... future will tell.
I didn't understand it the first time, so I asked maybe three times myself : I requote :
"You MUST use IIS BCK to divide down, not SIM BCK"
If you wait a little there should be a pcb from me or others with 4 layers according Thorsten's roadmap.
For your 2 layers question, there is a guy which have 20 years of experience and use it with hybrid starground and islands : Pedja Rogic. That's my today's reference at home aya2 2014 (modded front end with high end clocks and some trickies caps modes known as Eldam modes in Aya2/4 manual and some others writed nowhere). There is a GB for 45 euros the unpopulated board on his site (Aya5) with toshiba's dicrete I/V diamond like. Till now better than all you can find here. We have good expectations for the one to come here... future will tell.
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Edit : "You MUST use IIS BCK to divide down, not SIM BCK" ... which I understand as : if you use the Simutaneous mode you can not take the Bck signal for avtive FDEM at the feet of TDA1541A pin 2, but before the simultaneous mode circuitry. Many cpld Sim third party USB/Spidf with sim mode may use stop clock too which could be tricky for the pcb active FDEM. I planned to add SMA & UF-L possibilities.
Obviously I try to understand first and then solder, but I'm not very Expert with the concepts of digital electronics, and I won't deny that I've already gotten lost several times here in the forum. However, if my questions annoy or are OT i will remain silent and observe without any rancor. I will wait for the final PCB to come out and I will be very happy to thank you all of course. Ah ... I forgot, sorry for my English translated with Google.
All released "Marks" of the AMR CD-77 also do that.
Bottom layer links to pin 14 and is a solid DGND Plane.
Top layer highlighting the AGND Island.
Even the never released V7 Digital board for CD-77 stayed 2-Layer! It was fully prototyped, but the product was cancelled before the PCB got RTM'ed.
Here the schematic around TDA1541 that was used:
I suspect some if now looks very familiar as a lot parallels what we have been discussing here (and some does not).
This version had SMD decoupling cap's below the PCB:
This has more "islands" etc. but we can see how "cut up" the ground layers are.
It is possible on 2 layers, but 4 layers are more elegant and simple to make.
Thor
It is not that. But if someone asks you how to get Biscotti with their Caffe, you can send them to Caffe (MUG in Trieste is nice), you can give a recipe or you can explain from the point where you sow wheat.
A lot here is "start by sowing wheat" type answers. So we all need to recalibrate our answers towards "easy recipe with everything store bought".
Thor
I think you have right...but please remember that Bari is much more better of Trieste...so if you will fly in Italy next time, please don't forget to visit Bari
and meet me too of course.😊
A few years ago I was in Altamura, very nice place. But my daughter lives in Trieste so I go there more often.
Thor
This schematics is already a VERY solid implementation of TDA1541A peripheral.
Cheers
ThanX. Based on the file date, 15 years ago.
Rest was...
WM8805 in HW mode as SPD input, isolated input. Basic XMOS USB2SPDIF via WM8805. Nice 12MHz clock and power.
Alternative CD Drive on crystal.clock, Philips chipset, Sony mech.
CPLD for signal massaging, routing etc., SRC419X operated synchronous as digital filter / upsampler.
The ECL signal conditioning from the earlier versions was deleted. Main reason was that a number of parts from the original design had become unavailable.
Alas, it was decided to use up existing stocks of the CD-77 parts and cancel the product.
Thor
Thanks for sharing!
can you say a bit more about the output stage based on 6072a? 10 years ago I attempted to make my own, curious to see how far off i was 😊
can you say a bit more about the output stage based on 6072a? 10 years ago I attempted to make my own, curious to see how far off i was 😊
The one from CD-77 I posted here before. Not much to see really:
The "sound" is really mainly in the tubes and output cap.
My later one was based on the "Universal Tube Stage" I had designed for diyhifisupply.
Straightforward 6072A with a "ring of two" CCS anode load using a N-Channel FET (IRF710 or something like that). Output from Fet source. Pretty boring. I did not retain the design files after my cooperation with diyhifisupply ended, the principle is shown here:
Thor
Can I ask what is the purpose of the section dac_outR/L - Q6/7/8 - VDD at the very top of the schematic? Is that a CCS (I thought the output stage was negatively biased using -2mA idle current)?
On the AMR CD-77 the gain is moderately low. And the I/U conversion resistor the highest permissible value (or own tests), so offset current compensation was neccesary.
The later version on the basis's of Thomas's DAC with 6072 on the UTS board used "near zero bias".
Thor
Hi,
CD-77, TDA1541A, output L/R what does it see (looking out) in terms of impedance (typically, or otherwise ranging) and what is the value of I/V resistor (not shown).
To be sure; SIMdata source, NOT stop BCK, taken BEFORE any attenuation - can use this (divided) to synch DEM without penalty??
Cheers to all.
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68R // 22nF (~ 100kHz -3dB)
Yes.
Again, for the clock source for DEM (via divider) the rules are:
Continous clock. Clearly defined and constant relationship between clock frequency and desired FDEM. Suitable logic level for the logic you use.
Thor
68R with current inj. Same as 33R without, yep (?)
Use SIM BCK for DEM if stopped and NOT attenuated.
Clear.
Use SIM BCK for DEM if stopped and NOT attenuated.
Clear.
34 Ohm, but essentially yes.
You mean "Use SIM BCK for DEM if NOT stopped and NOT attenuated?
Thor