I have some USB to I2S adapter, will try it.
My understanding is that R data is latched when WS is high, and L data is latched when WS is low. There is 1/2 WS period delay between these events, so the analog output should follow it. (Why I see 1 full WS period between the channels instead of 1/2 WS period is still a question).
I don't mind it because the delay is inaudible, but technically I can't subtract R-L and inspect the residual signal. Or create L+R and see the distortion.
My understanding is that R data is latched when WS is high, and L data is latched when WS is low. There is 1/2 WS period delay between these events, so the analog output should follow it. (Why I see 1 full WS period between the channels instead of 1/2 WS period is still a question).
I don't mind it because the delay is inaudible, but technically I can't subtract R-L and inspect the residual signal. Or create L+R and see the distortion.
This is not about I2S signaling but how TDA1541 processes I2S data. That is specified in TDA1541 datasheet:
"The converted samples appear at the output, at the first positive going transition of the bit clock signal after a negative going transition of the word select signal."
I have a question a bit off-topic
Mr. Thorsten once mentioned a 6-layer board for TDA1541
My question is more general - for DAC
How should the layers be arranged looking from the TOP layer
In what order should the grounds, power supplies, etc. be?
I searched but it's hard to find a single sentence in thousands of entries....
BTW - I am full of admiration for your work and knowledge
Mr. Thorsten once mentioned a 6-layer board for TDA1541
My question is more general - for DAC
How should the layers be arranged looking from the TOP layer
In what order should the grounds, power supplies, etc. be?
I searched but it's hard to find a single sentence in thousands of entries....
BTW - I am full of admiration for your work and knowledge
Ok, so I sat down and pulled all the various strands of discussions, greatly appreciated input from @lcsaszar etc. together,
So if we make a PCB I suggest this:
I decided to bring a lot of stuff on board, simply because it places control into our hands, which I had left off originally. The inputs are now compatible with TLL variants and 2.5V -5V CMOS Logic.
The Shunt regulators are based on ones I have used multiple times before, the impedance is a few mOhm. Noise is the TL431 noise, which at 20uV RMS will seem high, however with the TDA1541 the PSRR is high enough this really doesn't matter at all.
Low impedance over the audio spectrum and beyond is by far more important. As shown the shunt regulators dominate up to ~ 35kHz. After that the decoupling capacitors take over.
The 1,000u Electrolytic (Os-Con here) & 1uF SMD Film (Panasonic, CDE etc) keep impedance well controlled. Additional bypassing does not help. As is the impedance of one of the 5V rails looks like this:
The peak ~ 1.4MHz will coincide with 88kHz sample rate @ 16 Bit BCK so it is of some concern, but it's still only at a fraction of 1 Ohm.
I suggest the following adjustments to make a PCB:
U4 can be 7824 or LM317 (TO220) (or any of many others)
U7 can be 7805or LM317 (TO220) (or any of many others)
All the flip-flops get a TH & SMD (SOIC) double footprint, so any number of 74XX74 logic families can be used. The (obsolete) 74F74 logic shown is non-saturating bi-polar logic (you CAN read that as "kinda Class A logic" ) comparable a little to what is inside the TDA1541. It is capable of 125MHz clock for flip-flops and adds only 26pS jitter. There are more modern CMOS logic options that add less, but most are chip scale SMD packages. A footprint for these could be placed below the PCB as well.
Add pin's to stack a 2nd PCB for a balanced DAC and selection for IIS/SIM operation of TDA1541 and L/R or balanced operation.
Signal lines to the 2nd piggyback PCB are from before the attenuators, power at the Os-Con. The second PCB is identical, but we do not fit all the logic IC and shunt regulators, it only holds a 2nd TDA1541, decoupling and signal attenuators.
The attenuators went back to a version of John Brown's, with higher impedance and no capacitor. After understanding the silicon level creation of the PNP input transistor better, I have more confidence into the 12pF input for TDA1541 capacitance being pretty low tolerance and not much signal dependent. Using our own logic here (74F74 with less voltage swing than 3.3V CMOS) makes sure we know exactly what drives our attenuator, again overall it is about controlling variables.
We had this discussion elsewhere, here is the stack-up I would use (4 layers are ok):
Top
Analogue signal and control signal routing, TH components & ground fill (with AGND/DGND split)
Inner 1
Ground planes (with AGND/DGND split)
Inner 2
Power planes (layer with matching GND planes)
Bottom
High speed digital routing, SMD components & ground fill (with AGND/DGND split)
AGND and DGND are split with a gap. AGND & DGND join at pin 14 only.
AGND and -15V on the Power layer are overlaid. Power supply "ground" connects at AGND.
AGND covers most of the space between the IV pins and to the right of the IC (datasheet view).
DGND covers the area between digital pins and the left of the IC and extends continuous to signal conditioning and inputs.
All SMD decoupling capacitors are placed inside the IC pins and connect to the relevant ground planes. It's pretty much as drawn, except they are not on the outside but inside the footprint, similar to this:
This layout and decoupling is BTW TDA1541 only, not "general DAC".
An ESS EX9XX8 or TI PCM1792 needs different approaches. There is no "one size fit all" approach that suits all DAC IC's.
Thor
PS, next, Ascendant Version, dual TDA1541, Super capacitors, analogue and digital supply split.
PPS, recommended AC supply section:
So if we make a PCB I suggest this:
I decided to bring a lot of stuff on board, simply because it places control into our hands, which I had left off originally. The inputs are now compatible with TLL variants and 2.5V -5V CMOS Logic.
The Shunt regulators are based on ones I have used multiple times before, the impedance is a few mOhm. Noise is the TL431 noise, which at 20uV RMS will seem high, however with the TDA1541 the PSRR is high enough this really doesn't matter at all.
Low impedance over the audio spectrum and beyond is by far more important. As shown the shunt regulators dominate up to ~ 35kHz. After that the decoupling capacitors take over.
The 1,000u Electrolytic (Os-Con here) & 1uF SMD Film (Panasonic, CDE etc) keep impedance well controlled. Additional bypassing does not help. As is the impedance of one of the 5V rails looks like this:
The peak ~ 1.4MHz will coincide with 88kHz sample rate @ 16 Bit BCK so it is of some concern, but it's still only at a fraction of 1 Ohm.
I suggest the following adjustments to make a PCB:
U4 can be 7824 or LM317 (TO220) (or any of many others)
U7 can be 7805or LM317 (TO220) (or any of many others)
All the flip-flops get a TH & SMD (SOIC) double footprint, so any number of 74XX74 logic families can be used. The (obsolete) 74F74 logic shown is non-saturating bi-polar logic (you CAN read that as "kinda Class A logic" ) comparable a little to what is inside the TDA1541. It is capable of 125MHz clock for flip-flops and adds only 26pS jitter. There are more modern CMOS logic options that add less, but most are chip scale SMD packages. A footprint for these could be placed below the PCB as well.
Add pin's to stack a 2nd PCB for a balanced DAC and selection for IIS/SIM operation of TDA1541 and L/R or balanced operation.
Signal lines to the 2nd piggyback PCB are from before the attenuators, power at the Os-Con. The second PCB is identical, but we do not fit all the logic IC and shunt regulators, it only holds a 2nd TDA1541, decoupling and signal attenuators.
The attenuators went back to a version of John Brown's, with higher impedance and no capacitor. After understanding the silicon level creation of the PNP input transistor better, I have more confidence into the 12pF input for TDA1541 capacitance being pretty low tolerance and not much signal dependent. Using our own logic here (74F74 with less voltage swing than 3.3V CMOS) makes sure we know exactly what drives our attenuator, again overall it is about controlling variables.
We had this discussion elsewhere, here is the stack-up I would use (4 layers are ok):
Top
Analogue signal and control signal routing, TH components & ground fill (with AGND/DGND split)
Inner 1
Ground planes (with AGND/DGND split)
Inner 2
Power planes (layer with matching GND planes)
Bottom
High speed digital routing, SMD components & ground fill (with AGND/DGND split)
AGND and DGND are split with a gap. AGND & DGND join at pin 14 only.
AGND and -15V on the Power layer are overlaid. Power supply "ground" connects at AGND.
AGND covers most of the space between the IV pins and to the right of the IC (datasheet view).
DGND covers the area between digital pins and the left of the IC and extends continuous to signal conditioning and inputs.
All SMD decoupling capacitors are placed inside the IC pins and connect to the relevant ground planes. It's pretty much as drawn, except they are not on the outside but inside the footprint, similar to this:
This layout and decoupling is BTW TDA1541 only, not "general DAC".
An ESS EX9XX8 or TI PCM1792 needs different approaches. There is no "one size fit all" approach that suits all DAC IC's.
Thor
PS, next, Ascendant Version, dual TDA1541, Super capacitors, analogue and digital supply split.
PPS, recommended AC supply section:
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Thank you Thorsten for the shematics refreshing..
No more +5V pin decoupled to Agnd but the distant 1200 uF/Agnd decoupled and still the +5V pin decoupled to DGND
No more -5V TDA pin decoupled to Agnd. (100 nF)
Both are changed by 1 uF across +5 & -5V
No more -15V TDA pin decoupled to -5V (100 nF) also ?
In the more classsical layout till today, decoupling just the -15V pin (Agnd since today in the orthodox canon) always gave me better result, avoiding in the same time to decouple +/-5V locally. Could it be the same in the new paradigm ? 0.1 uF to 0.2 uF acrylic rigth at pin 15 across -5V is worthing a try ? I would layout a free cap pad here to -5V just in case in my pcb.
So same flip flop reference for the front end and FDEM ,can be a 24 pin package 🙂 low power CMOS or less voltage swing (74F74 serie). TTL still possible (and better ?)
No more +5V pin decoupled to Agnd but the distant 1200 uF/Agnd decoupled and still the +5V pin decoupled to DGND
No more -5V TDA pin decoupled to Agnd. (100 nF)
Both are changed by 1 uF across +5 & -5V
No more -15V TDA pin decoupled to -5V (100 nF) also ?
In the more classsical layout till today, decoupling just the -15V pin (Agnd since today in the orthodox canon) always gave me better result, avoiding in the same time to decouple +/-5V locally. Could it be the same in the new paradigm ? 0.1 uF to 0.2 uF acrylic rigth at pin 15 across -5V is worthing a try ? I would layout a free cap pad here to -5V just in case in my pcb.
So same flip flop reference for the front end and FDEM ,can be a 24 pin package 🙂 low power CMOS or less voltage swing (74F74 serie). TTL still possible (and better ?)
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I would add full IC with 2 F-F to each line. Because of the metastability and to not share each F-F in the same package with different Fo.
And maybe ballanced receiver for MCK for recklocking all these F-F. 4-8 F-F.
Anyway, almost all digital ICs are capabile to drive up to 16 digital inputs?
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I was thinking about decouplig input format pin, but I just spot that You already done it with 1uF. 🙂
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Hi Zoran, you mean 8 different flip flop ics ?
BTW, 74F74 still exists in smd package ?!
BTW, 74F74 still exists in smd package ?!
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Yes but only in register.
there is no events in 1/2 period of WS (LE)
After L and R stored, after full LE period coming the event from HI to LO of WS, and that event trigers booth L and previously stored datas for sample at output.
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If we have something on 1/2 of WS it will be double samplig rate frequency...
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Like You said there must be a problem with programming arduino, and with other standard I2S outout device trere will be no delay L-R?
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No only 4 x 74F74 ICs.
Each 74F74 has 2 x F-F inside, just cascade in serial 2 x F-F for each line instead of 1 F-F.
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I will post the sch. Maybe a was already posted it i dont know?
Yup, DGND only.
For audio frequencies only.
Nope, again, DGND.
Yup. Actually
2 x 1uF film +5V > -5V
2 x 1uF film +5V > DGND
2 x 1uF film -5V > DGND
Nope, low frequencies only.
It is exactly that.
I doubt it.
Never hurts to have options.
TTL and LSTTL is too slow, except for the second pair of Flip Flops in the DEM circuit. 74HC is also slow.
I think 74F74 is the best compromise.
Thor
I was wrong at looking at the parts disponibility, there are still 74F74 and also in smd package 🙂 .
So all is perfect is a perfect world ! 🙂
In my experience this is not needed.
Never observed it in reality, solution to a theoretical problem.
Edges will line up anyway. So such separation doesn't really help.
Non of what I intend to use features differential clocks.
Currently we debate (off thread) to embed a pair of clocks. Being annoying I'll likely vote for clock'o'jocko or perhaps a pair of discrete J-Fet (R-Clock) clocks.
16 fan-out is a bit much. In my case we have only two MCK pins, Super fast Schottky TTL.
I am not as such decouple this pin, but -5 V which it is linked to. This way I get a row of 4pcs 1uF caps starting at "pin 29" which of course doesn't exist. They bond to DGND.
Thor
So, you confirm exactly what I wrote.
Urban legend. For the TDA1541. And for "Conversion".
Now A DAC with fast CMOS logic, or a digital filter with fast CMOS logic, that's another kettle of fish.
Note the datasheet does not mention "conversion". Just LE Jitter induced by ground bounce.
In the TDA1541 the PNP input transistors operate in class A between +5V and -5V, not GND and it doesn't directly determine the slicing level for the inputs.
The "slicing level of the TTL2ECL converter is set in a NPN differential Amp biased from DGND towards -5V.
So BCK induced noise doesn't really do much to to LE switching in the TDA1541.
Thor
Yes, TH & SMD (SOIC-14).
Ti has it active, Mouser has multiple ku Stock in either case.
Thor
Indeed, I tried with a Weiliang 24-bit USB device (USB in, I2S out) and Audacity, and the channels are in phase.
Yes, and with no guarantee that because something measures better, is technically perfect, that it will sound better.
Well, I havent seen any measurements in real life nor any technical perfection in those speculations , not to mention any pleasant sound , I am eager to see what all those contradictory things will produce , that said the -15 v reference was the best joke ever ......
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I would say evidence based interpolation of what we know for certain, what we observe, what we know about silicon IP that likely ended up inside the TDA1541 and comments from a few people who had more direct access.
To a large degree, what we have discussed and tested here, validated the design I made for the AMR CD-77 (it's in the thread here), but some simplifications are possible and some improvements are.
This is not per se about how something measures, but about understanding the mechanisms by which the systems works and the mechanisms of the undesirable features.
Reducing the feedthrough from the digital input into the substrate will likely have minimal difference on measured results, does it make a sonic difference?
Thor