Yes, jlcpcb or group buy. Project is open source.
Yes, if you can, there is still an unknown of what -5V actually does in the chip.
Something like this? https://zeptobars.com/en/read/Ti-NE5532-real-vs-fake-opamp
Due to different currents flowing in all pins, certainly the -5V have a role. Perhaps also for the upper or middle transistors not seeing full -15V voltage, and the different level bias.
Okay, after sleeping on this a bit, it's really, really bad practice to rely on a components parasitics for a fundamental circuit function. Moreover parasitics that are input signal variable and not documented.
So instead combining a high impedance signal conditioning network at the TDA1541 input pins, we need to make the network lower impedance and add lowpass capacitors. Sadly this now means circulating currents from, the CPLD become large enough to be a problem at over 1mA PP per line for each input, at up to BCK frequencies.
So a really solid ground plane with at nest 5inch or so distance between source or multiple larger diameter coax screens must carry this current. No ribbon wire etc, allowed and coax if of significant length must be correctly source terminated.
It might be better to place the whole signal conditioning at the source end and make it matched impedance for the coax or traces to TDA1541, but that blows up the "core module" concept.
Anyway, on second thought, we end up with this:
Alternatively, placing the same attenuator/slew rate limiter circuit at the source we would use values scaled to give ~50R out (240R series/270R to 5V / 75R to GND / 220pF).
The very high impedance Attenuator circuit from the earlier can likely also be used, but it may need adjusting the resistances to either higher or lower for correct operation.
I guess run 384kHz and see if everything plays correctly (slow piano listen for "rice crispies") and then check the output for BCK residue, adjust the circuit on BCK only until things work correctly and we see no BCK glitches, only LE and Data. Then replicate values across the other inputs and re-test. That process is probably a good idea for any untested attenuator circuit.
Thor
I would not sacrifice a working good chip.
But it would be interesting to reliably figure out the -5V.
I guess nobody ever got that zip file from Thomas and saved it somewhere?
Thor
Well, I will not get involved in making and selling boards. It's ultimately pretty simple. Simple enough to do without PCB on Veroboard.
Thor
Of course, otherwise there would be no current flow.
But it will not be part of the CM Logic running of +5V and it seems also clear it has no job on the DEM current sources.
So all I can make out is tail currents for the bit-switches, which need to be pull to 0V or a little below in order to kill current leakage from the bitswitches.
Normal CM Logic will not go much below ~1.5V, the tail CCS is usually biased with two diodes.
So there are likely level translators and current tails to -5V.
Each bit switch with level translation from PECL/CML may look like this:
Vcc = +5V, input is from standard CML.
Vee = -5V
PGND = DGND/AGND, not sure which
With a total of five diode drops in the chain, the +1.4V at the buffer transistor emitters become -1.6V at the base of the bit switch transistor.
Thor
I've wondered about that myself . . . I think he used to be a member here.
I think he used to run "diyaudiocraft" homepage . . . Can't find any information though.
Does anyone have Thomas' contact information?
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I used way mack machine to view www.diyaudiocraft.com pages from 2004 to 2006.
There is a link to a forum there. I found a post which had a mobile phone contact for Thomas.
I searched it in google and found reference to it being active as recent as 6 years ago.
Put the number into Whassap and it is registered to an owner who has a tube amp as his avatar.
Sent a message asking if he still has the big 1541A data paper - might get lucky.
There is a link to a forum there. I found a post which had a mobile phone contact for Thomas.
I searched it in google and found reference to it being active as recent as 6 years ago.
Put the number into Whassap and it is registered to an owner who has a tube amp as his avatar.
Sent a message asking if he still has the big 1541A data paper - might get lucky.
I think that digital inputs has to be isolated with some digital isolator. And after that recklocked. All that before attenuation prior to the TDA inputs.
Also every icoming signal additionaly should be isolated like BCK-I2S, MCK.
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THe isolators has to be single one, to avoid interefences of different F. Like IL71 type. I have good experience with ADUM1100 types.
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That is because the Analog output is also isolated galvanically trough the output capacitors after the IV buffer circuit.
That way ALL DA module will be isolated from digiral and analog side. And PS will .
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Why are You drifted from the 174.6KHz DEM pins decoupling Cs? You decreased the values?
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@ThorstenL and others
Which type of Flip Flop for recklocking You recommend based on the internal structure to match the ECL type inputs?
For DEM oscilator pins this is the "74F" series?
Which series for inputs, before attenuation?
Thanks
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Does this imply the use of through-hole components instead of smd?
Would using th components significantly degrade performance?
IME this is quite a job to get it right. These isolators are absolutely diabolical in terms of radiated EMI and jitter and variable time delay.
I absolutely refuse to work this hard for a one off build.
Isolate SPDIF using transformers and for USB use a USB 2.0 high speed USB Isolator.
Internally, if the TDA1541 and IIS2SIM sections (and clock if separate) have their own independent power supplies (competent designs re conducted noise) not linked to the source supplies there is no need for isolators. Adding is only "negetive magic".
????
Well, PECL with level shifters and / or attenuation makes the most sense for everything, PECL with 1.6V PP differential swing can probably be coupled directly into the oscillator pins via suitable capacitors.
I will use these simply because they are not CMOS and I want TH Parts for that.
PECL MC/SY100 etc. if SMT is used but that needs a lot of changes to the Attenuator/Slew rate limiter.
What I show assumes a standard LV CMOS (3.3V) 8mA pin as driving source.
Thor
No, it implies a combination. A 1206 capacitor is 3.2mm X 1.6mm so it fits well on a 3-hole/pad section of the board.
Where i specify SMD, yes.
Thor
Folks,
Elsewhere there is an off line discussion on TDA1541 Tube outputs. I quickly threw something into the Simulator. It's based on my experience with many tube based products, but untested and I will not build it myself:
The low gain of the 5670 or 6DJ8 (et al - these two and their variants are very similar electrically, very different pinout) means a bypassed cathode resistor and 62R I/U conversion with offset correction is needed to get 2V @ 0dBFS.
After the gain stage there is a sallen key filter and output buffer.
Optionally (close switch) there is a 3.2dB boost at 22.05kHz in the filter, to equalise the "SINC" (sic) rolloff of the DAC operating at 44.1kHz sample rate.
This filter will also "unfold" (in MQA-Speak) the hidden ultrasonic content encoded in the recording, with a final 3rd roll-off after the peak.
The CCS is feedback type for DC using TL431, but "open loop" for AC. So operating conditions are stable regardless of temperature etc. but the circuit does not rely on looped feedback for AC (> 1.6Hz). The 12V zener diode is turn on protection.
Performance? Well typically "ideal tube", ~0.1% HD at 0dBFS with almost pure H2. That is just the right amount of H2...
Katz's Corner Episode 25: Adventures in Distortion
Noise looks somewhere around -100dB.
I don't see a point of messing with tubes if you find this unacceptable, just an op-amp if you want really low distortion. The OP2156 would be my take, as Op-Amp I/U converter, plus sallen key filter similar to what is shown here.
Thor
Elsewhere there is an off line discussion on TDA1541 Tube outputs. I quickly threw something into the Simulator. It's based on my experience with many tube based products, but untested and I will not build it myself:
The low gain of the 5670 or 6DJ8 (et al - these two and their variants are very similar electrically, very different pinout) means a bypassed cathode resistor and 62R I/U conversion with offset correction is needed to get 2V @ 0dBFS.
After the gain stage there is a sallen key filter and output buffer.
Optionally (close switch) there is a 3.2dB boost at 22.05kHz in the filter, to equalise the "SINC" (sic) rolloff of the DAC operating at 44.1kHz sample rate.
This filter will also "unfold" (in MQA-Speak) the hidden ultrasonic content encoded in the recording, with a final 3rd roll-off after the peak.
The CCS is feedback type for DC using TL431, but "open loop" for AC. So operating conditions are stable regardless of temperature etc. but the circuit does not rely on looped feedback for AC (> 1.6Hz). The 12V zener diode is turn on protection.
Performance? Well typically "ideal tube", ~0.1% HD at 0dBFS with almost pure H2. That is just the right amount of H2...
Katz's Corner Episode 25: Adventures in Distortion
Noise looks somewhere around -100dB.
I don't see a point of messing with tubes if you find this unacceptable, just an op-amp if you want really low distortion. The OP2156 would be my take, as Op-Amp I/U converter, plus sallen key filter similar to what is shown here.
Thor
Add that price to the amanero clone, and it's better off to get jlsounds usb card which is fully isolated, and you skip two additional connection points. Ends up being the around ~ $. Well trialed and tested, to be probably the best one on the market for diy. Quality wise xing U30 should be on pair, but still it appears it has no full galvanic isolation. Maybe isolate on the dac board itself, could be cheaper, but desoldering sub connector, controlling impedance for isolator to board... Seems too much of a headache when a ready solution is present.
with modern isolators usb chips (Ti) not only the gnd is isolated but also the hot signals. It migth be important or not.
Can not we deal with EMC in the output of the power traffos with snubers and smd comom mode chokes to make it an acceptable level ? And relies on the full plan layers for the air one's origin ?
@Zoran : any smd reference for all the shift registers ? I would like to cope on smd for my core pcb design. So no Cmos smd exist ?
Edit, it is hard to source, but we should try to find a R-Core or O-Core traffo with a screen to gnd between primary and secondary whatever it is on the same core. I have some from the late Selectronic shop that were made in India and are excellent. Some may exist between the expensive made in Japan and the so-so chineese one. Traffomatic is a little expensive for where it is made imho (not real fair prices).
IME with TDA1541, R-Core made a great difference for all my actual TDA1541A Dac AYA2 2014 based with complex front end (4 PS just on that side).
Can not we deal with EMC in the output of the power traffos with snubers and smd comom mode chokes to make it an acceptable level ? And relies on the full plan layers for the air one's origin ?
@Zoran : any smd reference for all the shift registers ? I would like to cope on smd for my core pcb design. So no Cmos smd exist ?
Edit, it is hard to source, but we should try to find a R-Core or O-Core traffo with a screen to gnd between primary and secondary whatever it is on the same core. I have some from the late Selectronic shop that were made in India and are excellent. Some may exist between the expensive made in Japan and the so-so chineese one. Traffomatic is a little expensive for where it is made imho (not real fair prices).
IME with TDA1541, R-Core made a great difference for all my actual TDA1541A Dac AYA2 2014 based with complex front end (4 PS just on that side).
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This is imo the logical choice if wanting cpld made sim mode. Lyuben is a nice guy and give greave support (if you read me I didn't received the cpld ic yet : ) ).
As far I understand ! the clocks if after the galvanic isolation as it should but it is divided per two by the cpld on the clean side. So no reclocking after the cpld. Butthe jitter should be low enough for those old pcm chips and the JLsoundsLab layout is sota, the last one is very impressive ! Should outperform the chineese one. But of course cost perhaps twice than the chineese. But it is not gonna be a very cheap diy design. 6 layers cost, and there aare a lot of components.
One should not make imho a fake save on the front end, what is very cheaper is often more expensive, explained me one day a purchasing director in a complex project. Saidinlayman words : I am too poor to save monney here in such a project (and if I make a board I expect it at least pay its cost by selling few at fair prices if T. accepts, but perhaps one planned to publish gerbers ? @Brijac , @tonimxp , @Alexandre, @lcsaszar, @altor; @Alexiss @weissi , else? for the one wanting no verroboard and tapes I mean...
As far I understand ! the clocks if after the galvanic isolation as it should but it is divided per two by the cpld on the clean side. So no reclocking after the cpld. Butthe jitter should be low enough for those old pcm chips and the JLsoundsLab layout is sota, the last one is very impressive ! Should outperform the chineese one. But of course cost perhaps twice than the chineese. But it is not gonna be a very cheap diy design. 6 layers cost, and there aare a lot of components.
One should not make imho a fake save on the front end, what is very cheaper is often more expensive, explained me one day a purchasing director in a complex project. Saidinlayman words : I am too poor to save monney here in such a project (and if I make a board I expect it at least pay its cost by selling few at fair prices if T. accepts, but perhaps one planned to publish gerbers ? @Brijac , @tonimxp , @Alexandre, @lcsaszar, @altor; @Alexiss @weissi , else? for the one wanting no verroboard and tapes I mean...
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