Thanks Regal,
This would help to explain the perceived SQ. With less than ideal caps wrt leakage (8.2uf /3uA), it was hard to reconcile that the sound was so much better including substantially increased micro detail & quiet background over the 220nf film. Perhaps I am losing the least significant 5 bits, but they carry no practical information? It would be interesting to do an A/B test, but that is not easy given the need for mm signal path. Perhaps 2 caps soldered to the MSB and A/B on the ground return wire.
EC's Jitter Atten
Hi EC,
Could you please explain about this circuit? I'm thinking of for days but don't understand how it work and its effect. I used 74HC175 for reclocking in my TDA1541A DAC so far and would try apply your circuit on. But I don't understand it well.
Thx and Rdgs,
Art.
Hi EC,
Could you please explain about this circuit? I'm thinking of for days but don't understand how it work and its effect. I used 74HC175 for reclocking in my TDA1541A DAC so far and would try apply your circuit on. But I don't understand it well.
Thx and Rdgs,
Art.
Attachments
Art,
Have a read of this then write out a truth table. It helped me understand.
http://docs-asia.electrocomponents.com/webdocs/0cb4/0900766b80cb4d8f.pdf
Have a read of this then write out a truth table. It helped me understand.
http://docs-asia.electrocomponents.com/webdocs/0cb4/0900766b80cb4d8f.pdf
Galeb,
Impressive I must say!
As I will be going on this route over the next couple of weeks, I would be very interested in your clock design/layout...
-which did you use?
-how does it perform compared to solutions like Tent?
-what type of power regulation did you feed to the clock?
Thanks!
Clock things
Hi Studiostevus,
My clock design is an optimized Colpits oscillator. Because I have access to a simmetricon tester, I can see how does my clock perform. To design it, I use a special software, and I've adjusted the simulation to have an error of +-1dbc/hz respect to the real design.( The pcb design layout is done with this same software, wich one is used to design pcb's for cellular phones).
The supply has to be clean. I use 3 inductors of 1mh each, and 4 capacitors, the 2 firsts of 1000uf and the last ones of 10nf, forming an RC filter. All this section after a regulator of 9vdc, and 2 capacitors of 4.700uf, one before and the other after the regulator. I use the BFR92 for the oscillator. Special care must be taken when choosing the 2 capacitors for the crystal feedback, because of these ones, it depends a lot the noise quality of the design.
For now, I've reached -183,5 dbc/hz in my last design, and 0,2ppm with a fast discrete temperature control.
Don't know how does the Tent clock performs, but I've experienced that very low phase noise is vastly more important than very low ppm.
Sorry, but I can't post schematics, this is a research work for an audio company and it has copyright.
Hope this helps a little.
Hi Studiostevus,
My clock design is an optimized Colpits oscillator. Because I have access to a simmetricon tester, I can see how does my clock perform. To design it, I use a special software, and I've adjusted the simulation to have an error of +-1dbc/hz respect to the real design.( The pcb design layout is done with this same software, wich one is used to design pcb's for cellular phones).
The supply has to be clean. I use 3 inductors of 1mh each, and 4 capacitors, the 2 firsts of 1000uf and the last ones of 10nf, forming an RC filter. All this section after a regulator of 9vdc, and 2 capacitors of 4.700uf, one before and the other after the regulator. I use the BFR92 for the oscillator. Special care must be taken when choosing the 2 capacitors for the crystal feedback, because of these ones, it depends a lot the noise quality of the design.
For now, I've reached -183,5 dbc/hz in my last design, and 0,2ppm with a fast discrete temperature control.
Don't know how does the Tent clock performs, but I've experienced that very low phase noise is vastly more important than very low ppm.
Sorry, but I can't post schematics, this is a research work for an audio company and it has copyright.
Hope this helps a little.
Thats very impressive!
LClock XO3 = -153 dbc/Hz
Tent clock = http://www.diyaudio.com/forums/digi...44mhz-low-jitter-clock-kit-8.html#post1804962
Maybe this article will be useful...
http://repository.tudelft.nl/assets/uuid:283c827b-7257-461a-9fce-b0c2e3b6f99f/TR-diss-1781.pdf
http://repository.tudelft.nl/assets/uuid:283c827b-7257-461a-9fce-b0c2e3b6f99f/TR-diss-1781.pdf
Hi Art,
The circuit attenuates I2S signals to low level signals that can still reliably drive the I2S inputs of the TDA154x. TDA154x has current mode I2S inputs that are compatible with 5V TTL signals.
By minimizing signal amplitude, less RF energy is dumped into the chip internal circuits (reduced ground-bounce). This in turn helps to reduce related on-chip jitter levels.
In the MK7, BCK attenuator is driven by a divide-by-4 circuit and DATA / WS are driven by synchronous reclockers.
The I2S attenuator circuit is driven by an ultra high speed flip-flop running at approx. 2.4V power supply. Fast logic runs on lower power supply voltages in order to reduce losses / interference.
The voltage drop across the diodes equals 0.6V typical.
Output is logical zero, Q = 0, /Q = 1:
/Q tries to put 2.4V on the output through R5 (1K), but Q pulls this voltage down to 0.6V (D2 conducts). The output voltage for logical zero now becomes 0.6V.
Output is logical one, Q = 1, /Q = 0:
/Q tries to pull the output to 0V, but Q pulls it high (D3 conducts). However, the voltage drop across D3 will limit output voltage to 2.4 - 0.6 = 1.8V.
So the attenuator output will swing between 0.6V (logical zero) and 1.8V (logical one). The output signal amplitude equals 1.8 - 0.6 = 1.2Vpp. I attached a picture showing the BCK output signal.
I use these I2S attenuators on all I2S signals, BCK, WS and DATA.
The circuit attenuates I2S signals to low level signals that can still reliably drive the I2S inputs of the TDA154x. TDA154x has current mode I2S inputs that are compatible with 5V TTL signals.
By minimizing signal amplitude, less RF energy is dumped into the chip internal circuits (reduced ground-bounce). This in turn helps to reduce related on-chip jitter levels.
In the MK7, BCK attenuator is driven by a divide-by-4 circuit and DATA / WS are driven by synchronous reclockers.
The I2S attenuator circuit is driven by an ultra high speed flip-flop running at approx. 2.4V power supply. Fast logic runs on lower power supply voltages in order to reduce losses / interference.
The voltage drop across the diodes equals 0.6V typical.
Output is logical zero, Q = 0, /Q = 1:
/Q tries to put 2.4V on the output through R5 (1K), but Q pulls this voltage down to 0.6V (D2 conducts). The output voltage for logical zero now becomes 0.6V.
Output is logical one, Q = 1, /Q = 0:
/Q tries to pull the output to 0V, but Q pulls it high (D3 conducts). However, the voltage drop across D3 will limit output voltage to 2.4 - 0.6 = 1.8V.
So the attenuator output will swing between 0.6V (logical zero) and 1.8V (logical one). The output signal amplitude equals 1.8 - 0.6 = 1.2Vpp. I attached a picture showing the BCK output signal.
I use these I2S attenuators on all I2S signals, BCK, WS and DATA.
Attachments
Hi Tazz,
If these caps indeed have 3uA leakage current, it is almost 50 times higher compared to the 0.061uA LSB current.
Problem is that the leakage current on the 6 MSBs (active dividers) won't be exactly the same and that the 10 LSBs (passive dividers) don't have this leakage current at all.
The result could be significant loss of (dynamic) resolution (up to 5 bits).
If these caps indeed have 3uA leakage current, it is almost 50 times higher compared to the 0.061uA LSB current.
Problem is that the leakage current on the 6 MSBs (active dividers) won't be exactly the same and that the 10 LSBs (passive dividers) don't have this leakage current at all.
The result could be significant loss of (dynamic) resolution (up to 5 bits).
Hi maxlorenz,
The negative outputs are just in anti-phase, DC voltage levels remain the same as with the in-phase outputs.
So you can use one reference for all 4 passive I/V resistors. So all 4 passive I/V resistors connect to this single voltage reference. L, /L, R and /R signals are tapped from these 4 resistors.
If you also want to add full-DC-coupling, an extra variable DC reference voltage is required that will then serve as "GND reference", similar as with the MK7 DAC. This voltage needs to be fine-tuned so it exactly matches DC level on the 4 outputs.
The negative outputs are just in anti-phase, DC voltage levels remain the same as with the in-phase outputs.
So you can use one reference for all 4 passive I/V resistors. So all 4 passive I/V resistors connect to this single voltage reference. L, /L, R and /R signals are tapped from these 4 resistors.
If you also want to add full-DC-coupling, an extra variable DC reference voltage is required that will then serve as "GND reference", similar as with the MK7 DAC. This voltage needs to be fine-tuned so it exactly matches DC level on the 4 outputs.