No problem, will add this to future schematics.
The bias is set as per "Oliver Criteria" in all cases. Although, it appears that this amplifier is quite happy under biased. Both in terms of overall THD and stability.
Hi David,
Yes, this project continues...
I'll make the commitment now, this project is going to run to the end... Have a good feeling about this design.
The plan is to get a prototype PCB made in China. It is so cheap to get 10 PCBs made, why not? Take advantage while China is still cheap. An option will be included for a Baxandal Cascode TIS. This provides an extra 15dB of loop gain in my amp. It does mean redoing all compensation though. But for 15dB extra feedback correction, it could be a worthwhile avenue to explore. My personal belief is that the Baxandall Cascode, in Edmond's original SuperTis, is a key feature of it's performance.
Then after the performance has been optimised, I plan to do another layout and then repeat the cycle until something "good" and stable is created. Other, features like the power rail MOSFET relays and DC servo will be added to the 2nd version. The 1st version will be used to get the core amplifier optimised and stable.
At present I am looking at SMD options. The temptation is that there are some nice semiconductors available only in SMD. For example, BC856BDN, BCX846BDW and, of course, the HN3C51F/HN3A51F transistors.
The layout is going to be based on Dr. Cherry's figure of 8 method. It seems to suit this type of amplifier.
Is your layout going to be SMD or through hole or a combination (like mine will be)? It will be interesting to compare our approaches at the end!
Seems this amplifier is now known as the "lunch-break amp".
Always needed a name...Paul
P.S. Going to experiment further with the CM degeneration bypass caps. Similar to cwtim01. There's always something new to try
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Hi Paul,
nice to see the progress!
I followed your asc-invitation and played a bit with the circuit. The loop gain behaviour around the input stage, between nodes Z0 and Zan, is really impressive.
What I'm wondering about, is the loop gain seen by the output stage. Input stage and "common-base VAS" are linearized by at least some amount of Miller input compensation, while the output stage is only included into the loop via R11. A probe e.g. between node out and R11 shows this loop gain. ULGF is around 3 MHz, and the phase maximum appears at a higher frequency. This is not as impressive as the "gain flattening" near ULGF, which you have achieved in the loops probed by Z0-Zan and In+-Out+.
Do you think that there still is a chance to improve somehow the behaviour of the loop gain via R11?
Kind regards,
Matthias
nice to see the progress!
I followed your asc-invitation and played a bit with the circuit. The loop gain behaviour around the input stage, between nodes Z0 and Zan, is really impressive.
What I'm wondering about, is the loop gain seen by the output stage. Input stage and "common-base VAS" are linearized by at least some amount of Miller input compensation, while the output stage is only included into the loop via R11. A probe e.g. between node out and R11 shows this loop gain. ULGF is around 3 MHz, and the phase maximum appears at a higher frequency. This is not as impressive as the "gain flattening" near ULGF, which you have achieved in the loops probed by Z0-Zan and In+-Out+.
Do you think that there still is a chance to improve somehow the behaviour of the loop gain via R11?
Kind regards,
Matthias
That is Edmond's belief too, as I understand it, makes sense.
I have not decided on whether to have the rail Fets as part of a separate, add on board but your path seems sensible.
...at SMD options. The temptation is that there are some nice semiconductors available only in SMD. For example, BC856BDN, BCX846BDW and, of course, the HN3C51F/HN3A51F transistors.
Have looked at those HN3xxx. almost as quiet as the best at mid frequencies and exceptionally low 1/f noise - excellent.
I also plan a combination SMD + TH board, more important is that it is double sided.
I don't entirely like Cherry's layout. Seems to me best not to take the speaker out next to the input.
With a double sided board the loop area can be reduced to the thickness of the board and the inductance reduced to nano-H.
Thickness can be reduced even further with extra layers but that should be totally unnecessary.
Seems this amplifier is now known as the "lunch-break amp".
There's lots of hype names, the "Ultimate" amp and so on, the "LB" amp is pleasantly discreet for a discrete amp.
Best wishes
David
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As you know, when you try to improve one loop it often affects the others adversely.
I have basically 2 loops so I created the double probe to check them both simultaneously so I could optimize the total result.
I suppose Paul's results illustrate the old principle that we tend to optimize what we can monitor easily, and he can't see all his loops at once.
He did ask for a triple probe but I didn't see the need at the time.
Perhaps a triple probe is the answer but it's a lot of interactions to keep control over.
This is my principle rationale to advocate a simpler loop structure.
I also suspect that 3 way feedback nodes are potentially a source of excess phase, practically never beneficial.
But TMC has a three way node and can work well, hmm.. is that because the last section is a buffer?
So I haven't worked this out yet, just wanted to kick the idea around.
Best wishes
David
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The distortion figures and spectra highly depend on the load. This means, that probably the output stage is main contributor; for me, this is a basic design target. (probably, because the loading of intermediate stages may have an effect, especcially with this topology).
Personally, I would therefore try to do the best for the loop including the output stage. As long as the rest is stable and does not exhibit e.g. common-mode distortion, it would be of secondary interest (for me).
Does Paul use TMC? I can't see that.
The signal injection into the feedback path by TMC is indeed a problem, if the loop gains are large. I'm still reasoning how I can resolve that in my NMC design without adding an extra isolation buffer (1 trannie plus 1 resistor).
Kind regards,
Matthias
Completely in accord. I just speculated about how Paul could have optimized the other loops and somewhat overlooked this one.
No, sorry I wasn't clear.
I criticised complicated loops but I included TMC as an example that they are not all bad. So I didn't want to make a blanket condemnation.
More that I wanted to write down an idea to make myself clarify it, and perhaps have a discussion.
Best wishes
David
Hi Matthias,
Thank you for your kind words about this amplifier.
You are correct when you say that the only loop around the OPS is via R11. This is why I questioned whether the stability shown in the Z0-zan loop is real. Think I need to get back to Bode's book.
Using crude tests in LTSpice the extra stability did not seem to allow more difficult loads to be handled.
You can get a small increase in open loop gain with smaller values of R11. I worry about the resulting drop in input impedance though. Could always use a bootstrap but don't think any more loops would be a good idea.
Have tried to optimize the loop around the OPS by moving Zo-zan probe to the position you mentioned. It was easy enough to move the ULGF point so that PM was maximized but when Z0-zan was moved back to it's original position the ULGF had moved out to 15MHz. Seems like trouble to me.
Maybe my compensation scheme is either incomplete or I have reached another "false optimum". Need to have a think again. And create a triple probe.
Thank you for taking the time to look at my design.
Paul
Thank you for your kind words about this amplifier.
You are correct when you say that the only loop around the OPS is via R11. This is why I questioned whether the stability shown in the Z0-zan loop is real. Think I need to get back to Bode's book.
Using crude tests in LTSpice the extra stability did not seem to allow more difficult loads to be handled.
You can get a small increase in open loop gain with smaller values of R11. I worry about the resulting drop in input impedance though. Could always use a bootstrap but don't think any more loops would be a good idea.
Have tried to optimize the loop around the OPS by moving Zo-zan probe to the position you mentioned. It was easy enough to move the ULGF point so that PM was maximized but when Z0-zan was moved back to it's original position the ULGF had moved out to 15MHz. Seems like trouble to me.
Maybe my compensation scheme is either incomplete or I have reached another "false optimum". Need to have a think again. And create a triple probe.
Thank you for taking the time to look at my design.
Paul
Hi David,
Looking at the Baxandall TIS, it appears to be a good efficient use of components as far as open loop gain is concerned. What worries me a little is how this will interact with the two pole bootstrapped shunts. This is why I want to allow for this option on the PCB. Very rough sims suggest it can work but need to build and test...
The HNxxxx devices are ideal for my front end. The extra Vce would allow for some scalability in power. Low Cob, low noise, reasonable hfe and matched. What's not to like. They don't cost much either and Digikey stock them. Did consider a THAT array but cost and what looks like low hfe put me off.
You have a good point about having the speaker out next to the input. Maybe a hybrid layout would be best. Was thinking that a 3 stage amplifier could have three figures of 8? PCB layout is such a vast subject on it's own.
Double sided is a must. Can't see how you can have a good layout on single sided PCB. Also, I'm trying to get as much of circuitry as possible onto the one PCB. It was one of my goals to keep the build as simple as possible. Even thinking of having the PSUs on the PCB as well. Having only ~22V rails means that the capacitors are quite small.
What is your opinion on vias? With SMD they are unavoidable.
I did totally forget about the loop through R11. And improving that loop does indeed adversely affect the other loops.
Need to create that triple probe. Could get a little complicated. Time to go "old skool" and get the pen and paper out.
Almost got the laptop rebuilt with a clean install of everything. Time that could have been put to better use.
Paul
P.S. LB Amp is a perfect name. Understated and not claiming to be the "ultimate"...
Looking at the Baxandall TIS, it appears to be a good efficient use of components as far as open loop gain is concerned. What worries me a little is how this will interact with the two pole bootstrapped shunts. This is why I want to allow for this option on the PCB. Very rough sims suggest it can work but need to build and test...
The HNxxxx devices are ideal for my front end. The extra Vce would allow for some scalability in power. Low Cob, low noise, reasonable hfe and matched. What's not to like. They don't cost much either and Digikey stock them. Did consider a THAT array but cost and what looks like low hfe put me off.
You have a good point about having the speaker out next to the input. Maybe a hybrid layout would be best. Was thinking that a 3 stage amplifier could have three figures of 8? PCB layout is such a vast subject on it's own.
Double sided is a must. Can't see how you can have a good layout on single sided PCB. Also, I'm trying to get as much of circuitry as possible onto the one PCB. It was one of my goals to keep the build as simple as possible. Even thinking of having the PSUs on the PCB as well. Having only ~22V rails means that the capacitors are quite small.
What is your opinion on vias? With SMD they are unavoidable.
I did totally forget about the loop through R11. And improving that loop does indeed adversely affect the other loops.
Need to create that triple probe. Could get a little complicated. Time to go "old skool" and get the pen and paper out.
Almost got the laptop rebuilt with a clean install of everything. Time that could have been put to better use.
Paul
P.S. LB Amp is a perfect name. Understated and not claiming to be the "ultimate"...
The current Z0-Zan probe relates to the total of feedback signals via the output stage and via the Miller input compensation path. Having an ULGF of 15 MHz in the latter one would not really bother me, as this loop spans only fast small-signal stages operating in class A. Of course, this requires that the output stage does isolate difficult loads well enough from this nested loop, so that its gain behaviour does not alter too much with changing amplifier loads. If I remember right, Bob Cordell used quite high ULGF in his MIC version; Edmond's Super TIS simulations show around 15 MHz (TMC-MIC).
Understanding whether your shunt compensation scheme around the pre-drivers does isolate well enough will be important. On the other hand, you have fast drivers and output transistors, and the common-base plus common-collector* kind of "VAS" should perform comparable to a common-emitter version -- except, of course, for the hopefully higher bandwidth facilitating MIC application. So, normally it should work somehow.
Kind regards,
Matthias
* this is my current understanding why the folded cascode performs that well in terms of HF behaviour
Hi Matthias,
Thank you for this reply. It has straightened a few things out in my mind.
The first was the probe positioning of Z0-Zan. It now makes sense to me why the ULGF when Z0-Zan is between the summing node and the IPS is so high and not necessarily a problem.
Have now tried to optimise the loop around the OPS. Having Z0-Zan between R11 and the node out. The amplifier is now a little more stable into difficult loads.
You are right to be a little concerned about the shunts. They do cause a problem. Without the bootstraps the amplifier is rock solid into any load. directly connected to the OPS emitter resistors. But this destroys the open loop gain. Need to have a think about how to solve this without losing the bootstrapped shunts.
The Cascode TIS does appear to be fast enough to allow for the safe use of MIC. Can't see any problems here. Need to have a think about the OPS and the shunts though.
Have been wondering whether it is the unity current gain of the cascode TIS that allows it to be so fast? Could be wrong, but is it the Current Gain Bandwidth Product of the TIS transistors that counts here? So low current gain means that very high fT is possible?
Paul
The stability shown by Z0-Zan loop is real.
One way to think of this is that a 3 section amp has 3 three bits that can oscillate so there are 3 different return ratios to check.
In most cases the 3 return ratios are not independent so it is only required to check 1 or 2 loops but these are a limited subset of the problem - and since you like complicated multi-way feedback interconnections....
The position where it was tests the stability of the IPS section.
(Makes sense because it's at the input to the IPS)
Because this is a fast loop a ULGF of 15 MHz is not unreasonable.
Tests at all three points will reveal any effect of this imteraction on the resultant stability
I have some lower Vce, monolithic devices that look better for the current mirrors but the HNxxx look very nice indeed for the inputs.
Would eliminate the need to have over volt protection for the front end.
My 80 Vce devices are just a bit close to what I need for the 600 W@4 woofer amp module.
I don't really have an opinion on vias, what is your concern?
Best wishes
David
engrlvtn, your question is now here,
http://www.diyaudio.com/forums/solid-state/269330-help-first-amplifier-design.html
Hi Paul,
.
With common-base operation, all this trouble goes away, but there is only voltage, no current gain. Therefore, a pre-driver probably cannot be avoided. Now, we have the high-impedance node at the input of this pre-driver, and it is inside of the MIC loop ...
So, Edmond Stuart does some funny things there, as you do.
But alltogether: I think, the basic ingredient is the common-base operation with low input impedance and almost no intrinsic Miller effect (the grounded base isolates input from ouptut).
Kind regards,
Matthias
thank you, it's the same for me. A good discussions is beneficial and fun for allThank you for this reply. It has straightened a few things out in my mind.
.In my understanding, its the common-base operation of the cascode transistors. The low input impedance does not create a node like at the input of a standard common-emitter "VAS". In the common-emitter-case, you have a high-impedance-node at the input (high output impedance of current mirror and high "VAS" input impedance) which gives a pole at relatively low frequency. Miller compensation around the "VAS" shifts this pole away to higher frequencies ("pole splitting" property). With MIC instead of standard Miller compensation, you have to take care of this disturbing pole in another way. In Bob Cordell's book, there is a shunt compensation at the "VAS" input.
With common-base operation, all this trouble goes away, but there is only voltage, no current gain. Therefore, a pre-driver probably cannot be avoided. Now, we have the high-impedance node at the input of this pre-driver, and it is inside of the MIC loop ...
So, Edmond Stuart does some funny things there, as you do.
But alltogether: I think, the basic ingredient is the common-base operation with low input impedance and almost no intrinsic Miller effect (the grounded base isolates input from ouptut).
Kind regards,
Matthias
Sorry, this is wrong.
The frequency of the input pole is reduced, it becomes the dominating pole frequency determining the global ULGF. The frequency of the pole at the "VAS" output is increased, since the output impedance is reduced due to the local feedback by the Miller capacitor.
Matthias
Hi Matthias,
I follow your logic and I think we really agree just that you have a much more in depth view point than me. Need to have more of a think...
Been doing some sims where I have added a 100nF load directly to the OPS emitter resistors. Then I adjusted the shunt compensation until it became stable. This was done without looking at any plots. The bootstsrapped shunts were in place. It turns out that the most important loop in this amplifier is the VAS loop. It needed 118 degrees PM and the OPS loop 98 degrees phase margin. The plots looked sub optimal with a bode step in the VAS loop and the ULGF happening before the PM peak. Gain margins were all healthy.
Would post a plot but the PC had to restore back to a point where LTSpice wasn't installed....
Shows there is hope.
Paul
I follow your logic and I think we really agree just that you have a much more in depth view point than me.
Need to have more of a think...Been doing some sims where I have added a 100nF load directly to the OPS emitter resistors. Then I adjusted the shunt compensation until it became stable. This was done without looking at any plots. The bootstsrapped shunts were in place. It turns out that the most important loop in this amplifier is the VAS loop. It needed 118 degrees PM and the OPS loop 98 degrees phase margin. The plots looked sub optimal with a bode step in the VAS loop and the ULGF happening before the PM peak. Gain margins were all healthy.
Would post a plot but the PC had to restore back to a point where LTSpice wasn't installed....
Shows there is hope.
Paul
matze said:
Do you mean a pole rather than a node?
The best analysis of this that I have seen is >Here. "...Op-Amp Compensation, a Control-Centric Tutorial"
Even if you already know about it, I recommend a re-read because it's excellent.
The point is that a "pole split" is inevitable, as a result of the way the return ratio is altered, it doesn't depend on the details of the circuit.
(His earlier title was ' "Pole split" considered harmful', an allusion to a seminal paper in computer science.)
I really like this perspective because it seems very powerful, even without detailed analysis it is possible to see the shape of the solution.
Best wishes
David
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I did mean node (... such a high-impedance node ...), but pole fits as well
. Have to learn to write shorter, less technical sentences.I will have a lock at it. If I remember rigth, you already mentioned it in the thread on "Pure Cherry" by kgrlee, and both of you were impressed.
Kind regards,
Matthias
Tian probe with parameter stepping
Parameter stepping is a nice thing, at least as nice as looking at different loops at the same time. I did think some time about it and currently have the following solution for the probe by Tian et al. The example is for 3 values in the stepping list.
; 6 runs
.step param prb list -3 -2 -1 1 2 3
; val1 to val3 are the three values (e.g. a voltage).
; sval is the parameter that is actually used at the component.
; val1 is active during runs 3&4, val2 is used in runs 2&5, and val3 in runs 1&6
.param val1=0 val2=2 val3=10
.param sval1=val1*(prb*prb-4)*(prb*prb-9)/24
.param sval2=val2*(prb*prb-1)*(prb*prb-9)/(-15)
.param sval3=val3*(prb*prb-1)*(prb*prb-4)/40
.param sval=sval1+sval2+sval3
The Tian probe values to plot are:
-1/(1-1/(2*(I(Vi)@3*V(x)@4-V(x)@3*I(Vi)@4)+V(x)@3+I(Vi)@4))
-1/(1-1/(2*(I(Vi)@2*V(x)@5-V(x)@2*I(Vi)@5)+V(x)@2+I(Vi)@5))
-1/(1-1/(2*(I(Vi)@1*V(x)@6-V(x)@1*I(Vi)@6)+V(x)@1+I(Vi)@6))
I'm wondering about rounding errors if the three values are very different.
Kind regards,
Matthias
Parameter stepping is a nice thing, at least as nice as looking at different loops at the same time. I did think some time about it and currently have the following solution for the probe by Tian et al. The example is for 3 values in the stepping list.
; 6 runs
.step param prb list -3 -2 -1 1 2 3
; val1 to val3 are the three values (e.g. a voltage).
; sval is the parameter that is actually used at the component.
; val1 is active during runs 3&4, val2 is used in runs 2&5, and val3 in runs 1&6
.param val1=0 val2=2 val3=10
.param sval1=val1*(prb*prb-4)*(prb*prb-9)/24
.param sval2=val2*(prb*prb-1)*(prb*prb-9)/(-15)
.param sval3=val3*(prb*prb-1)*(prb*prb-4)/40
.param sval=sval1+sval2+sval3
The Tian probe values to plot are:
-1/(1-1/(2*(I(Vi)@3*V(x)@4-V(x)@3*I(Vi)@4)+V(x)@3+I(Vi)@4))
-1/(1-1/(2*(I(Vi)@2*V(x)@5-V(x)@2*I(Vi)@5)+V(x)@2+I(Vi)@5))
-1/(1-1/(2*(I(Vi)@1*V(x)@6-V(x)@1*I(Vi)@6)+V(x)@1+I(Vi)@6))
I'm wondering about rounding errors if the three values are very different.
Kind regards,
Matthias
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Seems more complicated than necessary.
It's easy to have nested stepped parameters.
That is, the probe parameter nested inside a swept value, say a resistor value.
There is a "trick", that they must be the same block of text to ensure the parser nests them in the correct order.
If they are defined in separate statements then it's not sure which way they will nest.
Then you just use the already defined Tian() variable for the first value or if there is no parameter sweep.
I have a Tian2() variable defined that uses &2 and &3 and will show the second value of the swept parameter.
And so on, works with any number of instances of the swept variable, very easily.
Seems there should be some neater way to parameterize this, so it's Tian(1) and Tian(2), but I haven't been able to make this work.
It's not clear to me exactly how and when the parameter substitutions are done but it seems arrays are after the simulation run.
Similarly it's not obvious how to use Boolean variables to set parameters prior to the run.
Any ideas on this?
Best wishes
David
It is possible to nest 3 levels so it should be feasible to have two probes and still do a parameter sweep.
I've never implemented this, wanted first to solve the Tian(x) syntax and not have it all hard coded.
It's easy to have nested stepped parameters.
That is, the probe parameter nested inside a swept value, say a resistor value.
There is a "trick", that they must be the same block of text to ensure the parser nests them in the correct order.
If they are defined in separate statements then it's not sure which way they will nest.
Then you just use the already defined Tian() variable for the first value or if there is no parameter sweep.
I have a Tian2() variable defined that uses &2 and &3 and will show the second value of the swept parameter.
And so on, works with any number of instances of the swept variable, very easily.
Seems there should be some neater way to parameterize this, so it's Tian(1) and Tian(2), but I haven't been able to make this work.
It's not clear to me exactly how and when the parameter substitutions are done but it seems arrays are after the simulation run.
Similarly it's not obvious how to use Boolean variables to set parameters prior to the run.
Any ideas on this?
Best wishes
David
It is possible to nest 3 levels so it should be feasible to have two probes and still do a parameter sweep.
I've never implemented this, wanted first to solve the Tian(x) syntax and not have it all hard coded.
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