Yes I think the improvements can be real, it's classic Bode.
Need to think about Matthias' posts in detail, but I definitely like TPMIC.
It is what I have in my own development model, the only shunt is the one incidental to TPC.
One really needs to see this for it to hit home.
It makes sense to me too.
Aesthetics is a bit debatable but I like Pier Nervi's quote, to translate freely -
"I have always believed in the inherent aesthetic force of an excellent functional solution."
I think my PCB layout ideas looks pretty nice.
OK, that's the plan then
I have had a bit of a discussion with Damir (Dadod) about this in the last few days.
My development circuit is EF2 so I also need low Vbe.
I still don't have a solution that I am completely happy with, so I planned to start a new thread.
I have a friend who is a real "transistors and wires" expert and will see if he can come up with any improvements to an earlier idea of mine that he quite liked.
Best wishes
David
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Hi Paul,
probably, this is the topology I meant. In the schematic, R28 would be the "TMC resistor" from global output, and C13 and C22/23 would form the two branches to some inverting node (here inverting input) and "VAS output".
In my experience, in a conventional topolgy, TMC does work at least as well as TPC with respect to OPS linearisation.
TMC has the drawback, that it does not linearise the IPS, but this is here done via MIC. TMC has the advantage, that the second-order loop-gain characteristic is only seen by the OPS, and the global NFB loop has first-order characteristics which gives clean square-wave response of the whole circuit.
I cannot comment in detail on the problems with TPC+MIC. Only one thing: the second-order feedback network (in the the MIC loop) does cost you some phase margin in that loop, depending on how close the two frequencies are located.
If you use the TMC trick, then there will be some frequency, until where the OPS will influence somehow the response in the MIC loop. But probably, this frequency will be substantially lower than the ULGF in the MIC loop. So maybe, at least the MIC loop will be easier to get stable.
On the other hand, using TPC+MIC, the two MIC frequencies also have to be placed in such a way, that the global loop including the OPS may remain stable. This would mean, that in practice the frequencies should be separated by a fair margin: if one places both very high, then the OPS sees an ULGF comparable to the MIC-loop ULGF. So I repeat: cannot really comment ...
Kind regards,
Matthias
Hi Paul and David,
after some more reasoning, just one more point.
Mostly (in a "standard" amp architecture or even in my last NMC version), the TPC network built from 2 Cs and 1 R will feed a high-impedance-node in the circuit. If you combine TPC with MIC, it is feeding the rather low-impedance global negative input point.
Did you already consider this difference? Some time ago, I was already wondering whether this difference also has to be considered with "standard" MIC. Of course, the impedance only matters if the transconductance of the stage behind this point is finite. If there is an influence, it could be more important with TPC.
In your current version, the TPC network is feeding an impedance that could be compared with the case of "standard" TPC in a "normal" VAS architecture, but without Darlington VAS, i.e. with low input impedance. Would this work as intended?
Kind regards,
Matthias
after some more reasoning, just one more point.
Mostly (in a "standard" amp architecture or even in my last NMC version), the TPC network built from 2 Cs and 1 R will feed a high-impedance-node in the circuit. If you combine TPC with MIC, it is feeding the rather low-impedance global negative input point.
Did you already consider this difference? Some time ago, I was already wondering whether this difference also has to be considered with "standard" MIC. Of course, the impedance only matters if the transconductance of the stage behind this point is finite. If there is an influence, it could be more important with TPC.
In your current version, the TPC network is feeding an impedance that could be compared with the case of "standard" TPC in a "normal" VAS architecture, but without Darlington VAS, i.e. with low input impedance. Would this work as intended?
Kind regards,
Matthias
Hi Guys
Regarding the current sources: Self noted that in his blameless, where he penny pinched and used a single feedback BJT to control both CSs, that if the monitored current was for the VAS then the amp had better slew rate than if the monitored current was for the diff-amp.
The output current stability is better with the feedback CS than with the buffered-reference types.
In LINEUP's power follower (thread on this forum), changing the CSs from BJTs with LED base references to feedback CSs reduced THD and increased bandwidth.
Yes, the feedback CS incorporates gain in a local loop and no doubt this can effect the greater amp circuit and its loop. But, the speed of the CS can be enhanced by adding one tiny cap, provided the control BJT has a base-stop, as Self showed in his book in the slew rate discussions. This also reduces high-frequency THD.
I saw similar discussions here and there over the years, in WW, EDN and letters in various magazines, which at the time convinced me to only use the feedback CS. It is probably a common condition, where when you are told all the good reasons you should "do X" that then you "do X" and forget all the reasons why... That's me.
Anyway, in the context of all the fast amps people like to build here, it seems counterintuitive to use slothy devices for cascodes and for CSs.
Have fun
Regarding the current sources: Self noted that in his blameless, where he penny pinched and used a single feedback BJT to control both CSs, that if the monitored current was for the VAS then the amp had better slew rate than if the monitored current was for the diff-amp.
The output current stability is better with the feedback CS than with the buffered-reference types.
In LINEUP's power follower (thread on this forum), changing the CSs from BJTs with LED base references to feedback CSs reduced THD and increased bandwidth.
Yes, the feedback CS incorporates gain in a local loop and no doubt this can effect the greater amp circuit and its loop. But, the speed of the CS can be enhanced by adding one tiny cap, provided the control BJT has a base-stop, as Self showed in his book in the slew rate discussions. This also reduces high-frequency THD.
I saw similar discussions here and there over the years, in WW, EDN and letters in various magazines, which at the time convinced me to only use the feedback CS. It is probably a common condition, where when you are told all the good reasons you should "do X" that then you "do X" and forget all the reasons why... That's me.
Anyway, in the context of all the fast amps people like to build here, it seems counterintuitive to use slothy devices for cascodes and for CSs.
Have fun
LTSpice certainly suggests this is true.
Have to resimulate this amp withn ideal CCSs to see if there is anything to gained from investigating more advanced types.
Reminds me there was some discussion about the stability of the two transistor CCS on here. It was shown that the addition of a base resistor and a capacitor resulted in a significant PM increase. Is this relevant? Not sure. Needs more thought.
We all settle on our own preferred design ideas. It what gives each of us our own style.
Fully agree with you on slow cascodes. In my simulations slow cascodes cost stability. Only concern I have with cascodes is oscillation. Not fully up to speed yet on how to deal with such things.
Paul
Hi Guys
I've tended to avoid cascodes but tested it out in the front end of an amp running off 100V rails. Mostly it was an exercise to see if placing zeners in the collectors of the diff amps to take up voltage would be noisier than using cascodes. That part turned out to be the same.
The diff amps use BC550C/560C, rated at 45Vce. To keep the variety of BJTs to a minimum and therefore just use BCs in the front-end requires a double cascode. No problems here. I read Andrew Russell's article about oscillation in cascodes and reached a different conclusion than he did once I did some sims in LTspice. In his circuit, and as I see in most apps here, the cascode has its base tied to a zener, usually with a cap to ground. Andrew added a base-stop to reduce a very high oscillation in the 100s of MHz range. He found adding a small cap to ground from the base-stop/BJT junction helped, as well.
When I sim'd this, it made things worse. I tend to take a different approach to certain matters, and in this case I used a simple voltage divider with large caps to ground at each node. This worked much better without any base-stops/caps than with them. The only indication of potential instability is a small peak after the unity-gain cross-over, but usually below a reasonable gain-margin. This peak was turned into a shelf by adding an emitter resistor on the cascode tied to the amplifying device collector. Adding Re's on the second cascode made no difference. Increasing the Re value a bit made the shelf slope down. In my circuit 348R did this.
I think of the divider bias for the cascode as being "benign", as the Rs damp the bases of the two cascode BJTs and any noise from the divider is shunted to ground by 220uF or larger caps at each node. I believe it is a mistake not to have significant local filtering even for the output stage. better amp layouts will have the output stage within 25mm of the main filters, or if that cannot be accommodated, then significant local filtering will be emplaced.
The loop response with the double cascode compared to the zenered collectors was the same.
I think the basic problem is tying the cascode base to a zener diode. This requires an emmense cap to properly filter the self-noise of the diode. The diode is nonlinear, so it likely feeds through some strange frequency response effect to the BJT, so utlimately this is imparted to the amplifier.
Have fun
I've tended to avoid cascodes but tested it out in the front end of an amp running off 100V rails. Mostly it was an exercise to see if placing zeners in the collectors of the diff amps to take up voltage would be noisier than using cascodes. That part turned out to be the same.
The diff amps use BC550C/560C, rated at 45Vce. To keep the variety of BJTs to a minimum and therefore just use BCs in the front-end requires a double cascode. No problems here. I read Andrew Russell's article about oscillation in cascodes and reached a different conclusion than he did once I did some sims in LTspice. In his circuit, and as I see in most apps here, the cascode has its base tied to a zener, usually with a cap to ground. Andrew added a base-stop to reduce a very high oscillation in the 100s of MHz range. He found adding a small cap to ground from the base-stop/BJT junction helped, as well.
When I sim'd this, it made things worse. I tend to take a different approach to certain matters, and in this case I used a simple voltage divider with large caps to ground at each node. This worked much better without any base-stops/caps than with them. The only indication of potential instability is a small peak after the unity-gain cross-over, but usually below a reasonable gain-margin. This peak was turned into a shelf by adding an emitter resistor on the cascode tied to the amplifying device collector. Adding Re's on the second cascode made no difference. Increasing the Re value a bit made the shelf slope down. In my circuit 348R did this.
I think of the divider bias for the cascode as being "benign", as the Rs damp the bases of the two cascode BJTs and any noise from the divider is shunted to ground by 220uF or larger caps at each node. I believe it is a mistake not to have significant local filtering even for the output stage. better amp layouts will have the output stage within 25mm of the main filters, or if that cannot be accommodated, then significant local filtering will be emplaced.
The loop response with the double cascode compared to the zenered collectors was the same.
I think the basic problem is tying the cascode base to a zener diode. This requires an emmense cap to properly filter the self-noise of the diode. The diode is nonlinear, so it likely feeds through some strange frequency response effect to the BJT, so utlimately this is imparted to the amplifier.
Have fun
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Hi Matthias
This is a issue that I have indeed considered, so I was interested when you raised this in your first post.
The reason that I didn't immediately reply is that I still don't have this clear in my mind.
For instance, in a conventional LTP + current mirrors the source impedance is in the order of 100k to 1Mohm so why are we happy to load it down with the VAS feedback?
Just to say "the VAS is a transimpedance section that takes a current input" only describes the result of the low impedance load.
Return Ratio (Loop Gain) is a dimensionless quantity and as we follow around a loop the current gain Ai or Av will differ at each point dependent on the impedances.
The physics makes me think that the power gain is what should matter.
No power gain means no instability is possible.
My own development amp uses TPMIC.
The input node is made particularly low impedance by the choice of a low impedance feedback divider.
This not only minimizes noise but should push the input pole up in frequency and improve stability.
It seems to work well and I have some lop gain simulations >HERE< for comparison.
I haven't really considered this for Paul's amp but it is based on Edmond's SuperTIS and I have had a serious think about that.
It seems to work best with a very hi-Z OPS, while my whole point has been to develop a circuit that works better with a simple OPS.
So the topic is a core interest of mine, any ideas welcomed.
Best wishes
David
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My turn for a follow-up query.
Classic Fourier analysis proves the square wave response is determined by the closed loop response of the amplifier.
Won't this be set by the feedback resistive divider essentially identically for both techniques?
Best wishes
David
Classic Fourier analysis proves the square wave response is determined by the closed loop response of the amplifier.
Won't this be set by the feedback resistive divider essentially identically for both techniques?
Best wishes
David
You and Matthias are now stretching my understanding. Which is good. One comforting thing is that it is not immediately obvious to you. As it was not and still is not obvious to me.
Interesting that you mention using a low impedance feedback network. Have been experimenting with Matthias's idea and have noticed that the feedback network values affect the open loop gain and stability for a given ULGF. So far I have managed to equal TPMIC in stability and the amount of negative feedback. One bonus has been the slew rate has increased and square waves are cleaner.
This amplifier seems to need the two pole shunts to burn off some gain. I can get all sorts of compensation schemes to "work" to some extent as long as the two pole shunt is present. Without the shunts the ULGF is always out in the 10Mhz + region.
The cascode TIS does not like to loaded. A 3EF is essential for this design. If a 2EF is substituted then the performance of the amplifier collapses. The minimisation of TIS loading is part of my design methodology, hence, the 2 pole bootstrapped shunts.
Still need to build the second prototype. Struggling with visualising the layout of the Supertis front end while using power rails down the centre of the PCB.
Paul
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Really impressive. The gain is shaped in such a way that the phase behaviour is only as good as necessary in a rather small neighbourhood of the ULGF. Only this probably allows, that there are no phase dips below -180 degrees, but still a high loop gain at e.g. 100 kHz is achieved.
Wish I could shape the loop gain as good as you.
Kind regards,
Matthias
Hi David,
>I haven't really considered this for Paul's amp but it is based on Edmond's SuperTIS and I have had a serious think about that. It seems to work best with a very hi-Z OPS.....
Not just that, a very hi-Z OPS is one of the essential pillars of the SuperTis design philosophy (because one of the gain stages in the front-end has been omitted). Removing a gain stage from the OPS as well, will never yield a low distortion amp. Doing this violates the whole concept.
Cheers, E.
>I haven't really considered this for Paul's amp but it is based on Edmond's SuperTIS and I have had a serious think about that. It seems to work best with a very hi-Z OPS.....
Not just that, a very hi-Z OPS is one of the essential pillars of the SuperTis design philosophy (because one of the gain stages in the front-end has been omitted). Removing a gain stage from the OPS as well, will never yield a low distortion amp. Doing this violates the whole concept.
Cheers, E.
Hi Edmond
I do realize it is a part of the concept, I included the word "seems" only because I haven't actually tested it myself.
The reason my words were qualified is expressed in post #87.
When an LTP + Current Mirror input is loaded by a Miller compensated second section then that low impedance load is apparently no problem,
(I suppose one problem is that the Miller compensation turns the second section from a VAS to a TIS., and this creates interminable quibbles about nomenclature
)Cherry does discuss non-linearities in current gain as opposed to transconductance non-linearities, probably another way to consider the issue.
But it's still not clear to me when the lower Z load actually creates problems.
Do you have any comments on this or post #87?
Best wishes
David.
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Sorry for off topic but could someone explain why zero ohm resistors are used in circuits.
I've seen circuits with them, and thought them to be fusible or something,
so I took one and shorted it across my dc supply, lol, they don't fuse
Regards
Hi Vostro,
They are nothing but a wire link. I just find them easier to use than keeping the trimmings off components for wire links.
Paul
Hi Guys
It would be helpful if schematics posted here included the output stage idle current, since this seems to have a great effect on stability and performance. Ft varies with collector current and too low for either often leads to oscillation. However, sometimes we try to keep dissipations low and battle against this to achieve stability.
Have fun
It would be helpful if schematics posted here included the output stage idle current, since this seems to have a great effect on stability and performance. Ft varies with collector current and too low for either often leads to oscillation. However, sometimes we try to keep dissipations low and battle against this to achieve stability.
Have fun
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