This change makes the current flowing in the VAS indeterminate (not easily predictable by calculation). This means that the current change in the VAS for a change in the tail current of the IPS is increased. (Since the bias circuit of the OPS is only a resistor), the variation of the bias current of the OPS will inevitably also increase.
It is recommended that only the drains of the unused sides of the IPS (Q2 and Q4) should be connected to the emitter of the VAS.
I read through your posts again. I believe your build is with Vertical MOSFETs which is a different beast. If I swap Q7/8 with Bob Cordell's models for IRFP240 / IRFP9240, I get the same crossover artifact... until I adjust the bias. Once I bring the bias up, it goes away.
How are you checking the output bias?
How are you checking the output bias?
Hi Mason,
I believe you saying the VAS becomes more sensitive to changes in the tail current of the IPS. Do I have that right?
I'm checking in sims by stepping junction temperature and power supply regulation. I'm not seeing any issues.
I do see that the VAS current is more sensitive to ambient temperature changes. VAS current drops as ambient temps increase. Which in turn lowers output bias. This is for a sweep of 25C to 45C. I see this as a scenario where the temp inside the case rises excessively due to poor airflow. In this case, bias dropping probably isn't a bas thing. Lowering bias would reduce dissipation which should lower the ambient temp inside the case.
I'll keep thinking about this. Is there anything else I'm missing from your perspective?
I believe you saying the VAS becomes more sensitive to changes in the tail current of the IPS. Do I have that right?
I'm checking in sims by stepping junction temperature and power supply regulation. I'm not seeing any issues.
I do see that the VAS current is more sensitive to ambient temperature changes. VAS current drops as ambient temps increase. Which in turn lowers output bias. This is for a sweep of 25C to 45C. I see this as a scenario where the temp inside the case rises excessively due to poor airflow. In this case, bias dropping probably isn't a bas thing. Lowering bias would reduce dissipation which should lower the ambient temp inside the case.
I'll keep thinking about this. Is there anything else I'm missing from your perspective?
If I change the bias network from a resistor to simple transistor based (single 2N5551 at board level running at ambient temp), the OPS bias becomes very stable even with ambient temp changes. It drops slowly with increasing ambient temp. 600mA at 25C and 588mA at 45C.
Something to ponder now before boards get sent out for production.
Something to ponder now before boards get sent out for production.
Yes, that is correct.
I recommend that you vary the tail current of the IPS by varying VR1 and examine the change in the current flowing through the VAS at that time.
It is likely that the VAS is oversensitive to the extent that the VAS degeneracy resistor is not functioning.
I just checked my working channel on the bench. It was originally tested in my garage in the middle of summer when temps where around 100F. It's now 70F out there. I seem to remember the bias being in the 400 to 600 mA range. It now measures 90 mA. So maybe a transistor based bias network sensing ambient temps is a good idea.
I ran sims adjusting the VR1 trimmer by 100R for the original and revised designs. With the original, VAS current varies by 4mA. With the revised design it varies by 8mA. It increases, but it shouldn't matter. Once it's set, it shouldn't change. The JFET run cool and don't seem to be affected much by ambient temps or power supply regulation.
Here are some numbers to quantify the performance improvement of the revised design. The original sims at 0.035% THD at 20KHz / 25W. With the change it measures 0.025%. You might not care much about improvements at the edge of our hearing range, but this impacts IMD resulting in a 5dB to 6dB reduction in the 1Khz IMD component of a 19KHz / 20KHz CCIF two-tone test.
Yes, I have checked all currents. In SIMs this worked fine, I think I would have noticed such deformation earlier in the SIM. What I see is that for some reason I have the resistors on the VAS emitters being 47 Ohms. Not sure why I raised from 27 (probably for lowering the current in the VAS, I am using TTA004B and TTC004B). When I lower that, the artefact vanishes in the SIM.
Will check that now on the test build.
Measure the voltage across the vas degeneration resistors. You can use it to calculate the VAS current.
I’m fairly certain the notch you are seeing is crossover distortion from underbiasing.
Raising the IPS current raises the VAS current which in turn raises the OPS bias.
So, I think your issue is an under biased OPS and raising the IPS current price a resolving it. But the core issue is not the IPS current.
I’m fairly certain the notch you are seeing is crossover distortion from underbiasing.
Raising the IPS current raises the VAS current which in turn raises the OPS bias.
So, I think your issue is an under biased OPS and raising the IPS current price a resolving it. But the core issue is not the IPS current.
The output stage is definitely not under-biased. I can read that (almost directly) on the display of my lab power supplies. What I did not yet measure really is the VAS current. Will do check if it matched simulation.
Yes, I know. Initially, and when changing from 1mA to 2mA through the IS, I adjusted the OS bias.
Yes, I know. Initially, and when changing from 1mA to 2mA through the IS, I adjusted the OS bias.
Hmm. So you’re thinking the VAS is underbiased. That would make sense. It could be leaving class A causing the crossover distortion.
No, it is not underbiased. Currently runs with about 70mA.
Actually not sure what is wrong. Likely it is just my optimism to try with the verticals, because in my SIMs they looked promising 🤪 .
All changes making this go away in the sim have not yet worked in real life.
I will give it a shot with ECX10N20 and ECX10P20 next weekend or so.
Actually not sure what is wrong. Likely it is just my optimism to try with the verticals, because in my SIMs they looked promising 🤪 .
All changes making this go away in the sim have not yet worked in real life.
I will give it a shot with ECX10N20 and ECX10P20 next weekend or so.
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Some more tuning:
- Added an input low pass filter with R2 / C2. In addition to RF filtering, it seems to clean up the square wave response and still produces a symmetrical ±100 V/μs.
- Increased R1 from 100K to 221K. The low pass corner frequency of the C1/R1 and C3/R10 now match at 0.72Hz.
- Replaced the resistor-based bias network with a transistor-based bias network. Q9 is used to compensate for ambient temperature changes. This original design was sensitive to this, as I learned from bench testing (see posts 183 & 184).
- Thiele network R19 reduced from 10R to 2.2R. The reduction improves square wave response into capacitive loads. Spec'd at 3W as the PCB footprint readily supports this size.
Here's the update rendering. Time to sleep on it, then double check before sending off for production.
There's been a lot of changes from the original design. I'll work on getting the guide and BOM updated in the first post.
Nice work Brian!
The development of this project has taken many turns to get to this point.
The development of this project has taken many turns to get to this point.
Amen Brotha!
(That’s not literal brother🤣)
(That’s not literal brother🤣)