Transformer I/V converter combined with tube, an experimental circuit.
https://www.diyaudio.com/community/...output-stage-with-lundahl-transformer.100297/
https://www.diyaudio.com/community/...output-stage-with-lundahl-transformer.100297/
True, but CD-Players fitted with them remain available for low cost. And harvesting a DIL-28 IC from a single or double layer PCB is within the realm of possible for most DIY'ers.
But additionally finding a device with the correct CPLD/FPGA, unsoldering the 64-Pin LQFP SMD IC, hoping it was no write protected and can actually be written adds another layer of headaches.
Another year and it's gone too.
Thor
Thanks, so I am okay, I have connected the pins to +5V_Recl, I had a doubt cause I thougth it needed a resistor between them and the power plane.
The board I have made is w/o R18 between -15V and -5V, w/o pot to trim Vc_RECL (one has to check the good value to have the "rigth" voltage. It is the one published here, so with no pull up on the digital Le/Bck/DR/DL : https://www.diyaudio.com/community/...ate-nos-dac-using-tda1541a.79452/post-7822383
Sim boards :
Wuei is a nice guy, he answered me immediately and alas the little board is totally discontinued, so remains the sligthy bigger one you inked but that is a little bulky to my tastes but at least people have a choice for their needs. I don't like he idea at Alixpress the price is twicer than at Tobao when you don't live in China.
For simultaenous mode @miro1360 here have made a 2 layer cpld board with some logic as well as @raptorlightning . But we don't know how exactly yet the timing was chosen and it seems it can be tricky, as a reminder @Zoran linked that to me : https://www.diyaudio.com/community/...ate-nos-dac-using-tda1541a.79452/post-5697328 . Was about a bug on JLSOUNDS LAB; sim mode can work w/o a real interrest if not made the rigth way.
Should be programmed for off set binary : "Now conversion happens right in a middle of empty sample frame as it should" dixit MV Audio
For reference : https://www.diyaudio.com/community/...ate-nos-dac-using-tda1541a.79452/post-5697328
https://electrodac.blogspot.com/p/i2s-to-tda1541a-converter-tutorial.html (a balanced version exists)
All these 3 boards solution uses stop clock at the end. I2StoPCM board would not work so has been "disqualified".
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Years ago I asembled my nanocrystalline trafo, and I not remember the grade (too bad), but basically is not the high power electrical one; are one more delicate (not very high Bsat), like the one I tested for industrial Current Transformer.
Interesting, but since the most good for audio have lower maximum Bsat, so can inposes more turns for same low freq. power compared to the "mundane" GOSS, making it bigger and imposes more sectioning.
Zoran mentioned VAC cores. I just remembered that I got some strange Siemens telecom trafos from decades old, using VAC (or VAIC?) cores. Visually seemed to be some "noble" core like nickel or so, but perhaps they are for another applications and so another grade (edited for clarification)... some measured very high induced current distortion; others, do not.
Beautiful sectioned trafos here!More sections.
Standard minimum sectioning for quality audio (I do not consider multifilar winding suitable for audio, based on listening) is 5 sections P/S/P/S/P with 7 sections preferred. Windings should alternate clockwise/counter clockwise and screens should be placed between sections.
Horizontal sectioning (Scheibenwicklung) as common in germany is also possible:
Finally, each horizontal section can be vertically sectioned so a maximum of 6 X 7 sections can be wound.
Thor
Almost an art, since nobody modelled it on a computer for simulating it reliably or in ultmost detail. Initial knowledge are from old books...
All trafos I use in my DIY projects are self made (the projects), in toroidal form (since I worked in one toroidal trafo company).
Including the output for tube amps.
As we know, also with toroidals, a careful arrangement of layers are required for good response. Granted a lot of work...
I need to look closer, but that looks like zero-field with feedback. Nice idea.
I remember seeing something similar before. John Broskie perhaps.
You observe that the output signal is inverse of transformer ratio. That is because the SRPP actually acts as near short for the secondary winding.
Voltage across the secondary (actually primary to be precise but that needs negative load impedance) should ideally be 0, that is what zero field input circuits (incidentally invented during the communist year at the Hungarian State Radio & TV research group) means.
This more complex design you show could be simplified into something like this:
This uses a small 1:1 transformer and a voltage out DAC. The transformer secondary level is ~ 26dB less than it would be in normal 1:1 configuration. So LF distortion form the undersized transformer is much reduced. The circuit is a deliberate "Toobifier" with around -65....-70dB H2.
Why? See here:
Katz's Corner Episode 25: Adventures in Distortion
However the circuit is extremely tractable and can be applied in a multitude of ways.
Replace 1:1 with your Lundahl in 1+1 : 8+8 and we get 0.5mA PP (IIRC) with an I/U resistor of 22k that is theoretically 11V, of course the transformer DCR losses and the limited gain of our triode connected 6AK5 limit just how much gain and feedback really happens.
Using a 12AX7/6N2 CCS loaded gainstage (watch pinout) with a 12AU7/6N6 (watch pinout) follower (or perhaps a hybrid super mu-follower?) gives a lot of open loop gain with good open loop linearity. Then a good quality high step-up transformer can be used in zero field mode for low LF distortion and the tube circuit itself will work at high levels of shunt feedback.
Like so:
Thor
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Guys like Bisesik or the guy of Tribute became rarer...
And the virgin signal will meet sooner or later a ca pon the signal path after the dac at best...
But a power DAC and the price or non usefull Sowters here, but in the eyes of their customers (that bias shortcut) ; it is staying marginal developments. But good to know of course.
And the virgin signal will meet sooner or later a ca pon the signal path after the dac at best...
But a power DAC and the price or non usefull Sowters here, but in the eyes of their customers (that bias shortcut) ; it is staying marginal developments. But good to know of course.
I heard Jensen also used the virtual-gnd solution for some of these trafos.
EDIT: I'm not fully sure, since I'm looking and not find yet...
EDIT: I'm not fully sure, since I'm looking and not find yet...
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The CPLD is available at LCSC and current, so could go onto a PCB made by JLCPCB at a cost.
LCMXO2-256HC-4SG
If the coder remains on DIYA (which I believe he is) we could fix any bug.
Continuous BCK at 16 X FS not 64 X FS.
Soldering is a more than a little bitchy. No way I will do so by hand. That's a job for a PCBA Fab.
DEM Reclock is included.
So this CPLD can be embedded as option on the PCB, or a SAA7220 Footprint can and the board can be annexed as breakoff.
The SAA7220 footprint has the advantage that once that CPLD is nixed something else may be made and one might even approach Wuei to make a parallel version and plugin for SAA7220 using his CPLD. So a ready to run commercial solution also exists (I want one).
Thor
It was the D train entertainment TV ? 😍
Those guys danced so well, you wanted not to bring your wife here ! Lol. Good times.
Each time I see this show it is a reminder on how bad your own timing rythm can be bad !
Those guys danced so well, you wanted not to bring your wife here ! Lol. Good times.
Each time I see this show it is a reminder on how bad your own timing rythm can be bad !
Look again, it's not a 1:1 turn ratio for iout dacs. Give it more than just a glance 🙂 Very very good transformers for our purposes here.
Yep, and then you have them in non official sources, like tda1541a. As well as from used gear, again, like tda1541a. We aren't designing a dac to be made in large quantities. If needed, such good parts can be found new or salvaged from gear. Not backing off wm8804 😁
So this is basically I2S->PCM conversion with 16 BCLK/Sample. What is the I2S source? (USB/SPDIF etc)
No idea, not my work. But it's fully open sauce.
And if BCK is divided by 4 to get 16 X FS BCK the signal source must be 64 X FS BCK IIS, mainly what most USB bridges and SPDIF decoders output.
Thor
At his website all I found listed were 1:1.
Again, I'd like to see 20Hz HD before commenting more.
Again, TDA1541 is a chunky DIP part, easily handled by most DIY'ers.
WM8804/5 are NOT for manual hand soldering.
If we have a premade PCB that is stuffed with all fiddly SMD at JLCPCB or similar, it doesn't matter, any DIY'er can take the PCB and solder on the remaining TH parts and chances it works are high.
So I am in sisting on DIP/TH for any obsolete or hard to source parts, or "bog standard" Amanero format compatible PCB's from Ali the Express...
That's my logic for now excluding the WM880X.
It would seem putting AK4118EQ on board and optimising it is what's needed, unless there is another fire at the AKM plant.
How about an SPDIF receiver in FPGA?
Thor
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Yes, his website is luckluster and scarce, he states vout dacs 1:1, but no ratio for iout. Info is within the topic.
Theres amanero clone with wm8804 on it. So we can still keep the standard and have highest performing spdif (and still keep the onboard footprint/peripherals which is to my liking). And yes, i'm making the design with amanero footprint rather than jlsounds as a cheaper alternative, also as we will clock/reclock on the board itself so jlsounds benefit fades a bit, only i would suggest everyone to use U30 instead. Another note is that it is fairly simple to leave headers and jumpers for external spdif board like ak, or wm premade.
I have already gathered most components, as well as wm, and i can video how to hand solder it.
@eclipsevl : if you mind to make a board with the rigth offset binary timing for the simultaneous mode and think multichannel DAC to make an active 3 ways, and sell it a very fair price as I plan if interrest to cover the hassle and logistic, I'm sure you'll find some interrest from a small batch of people here to an active 3 ways loudspeakers made from the PC then towards 3 TDA1541A for the DAC.
Time clock seems unnecessary in T. design but I have low if any understanding here... up to you
That means HDMI to CPLD; 4x3 SMA or uf-l outputs for 3 simuktaneous boards or more pins for balanced...
But I like the idea of Thorsten made sift registers for a "discrete" discrete. A little like brick & mortar VS click & mortar spirit ! My watch is a Seiko five sport analogic, 100% made by one manufacterer (Seiko) ! I don't need software here ! But have nothing against an Apple watch (it is just not for me)
Time clock seems unnecessary in T. design but I have low if any understanding here... up to you
That means HDMI to CPLD; 4x3 SMA or uf-l outputs for 3 simuktaneous boards or more pins for balanced...
But I like the idea of Thorsten made sift registers for a "discrete" discrete. A little like brick & mortar VS click & mortar spirit ! My watch is a Seiko five sport analogic, 100% made by one manufacterer (Seiko) ! I don't need software here ! But have nothing against an Apple watch (it is just not for me)
Thinking out loud....
Ok, we are trying to make a solution for TDA1541. Ideally one we can connect to any old IIS source and get out nice audio, SMD work by some cheap chinese prototyping PCBM/PCBA contractor like JLCPCB.
We now have CPLD/FPGA with IIS2SIM that is likely to remain available a while.
I wonder if enough resources remain to integrate a FIFO to decouple output and input. 4 Bit, or 32 Bit, as long as possible.
We use simple crystals with switching between 22.5792/24.576MHz and add literally Micha "Brutalsky" Firer style totally brutal pull capacitors so we can let the crystal run as fast as possible (no caps), at nominal speed (nominal load) and al the slowest speed (maximum pull load). I think we can get at least +/50ppm pull range probably more.
We can do all that using RF relays, including improvised UB2/G6K wrapped in self adhesive copper foil. I just want to use "chunky stuff".
So now we have a low phase noise, precision oscillator we can trim digitally 50ppm fast or slow.
We get our CPLD/FPGA FIFO to give the HF (Half Full) and AF/AE flags (normally 1/4 or 3/4 point). Let's also have a 44.1/48 flag.
We start with default 44.1kHz base clock. We count the MCK cycles per WCK.
If it is an even multiple of 16 we keep the set clock, if it is less we step down the clock (unless we are at minimum) otherwise we step up one gear.
We have time to do that because we need to fill the FIFO.
At HF we start the output on our X-Tal MCK divided down, nominal clock load for "center" of clock.
Once we hit AF/AE we compare the HF flag to determine if we are AE (output clock to fast) or AF (output clock t slow).
If we are too slow, we trim our clock to "fast", else to "slow". Yes, each time we make a trim step, the output has a HUGE measured "jitter" but actually, it's just a clock trim, where over tens of milliseconds the oscillator will shift to the new frequency.
If our Fifo management cannot follow our source clock well enough, we switch local MCK off and use source MCK as lower quality but reliable fallback (more relays). In this case the FIFO & IIS2SIM section can also be omitted and jumpered out, for those with JLsounds USB, WM8805 SPDIF whatever...
I think this makes a great all in one TDA1541 PCB for 2025.
Thor
Ok, we are trying to make a solution for TDA1541. Ideally one we can connect to any old IIS source and get out nice audio, SMD work by some cheap chinese prototyping PCBM/PCBA contractor like JLCPCB.
We now have CPLD/FPGA with IIS2SIM that is likely to remain available a while.
I wonder if enough resources remain to integrate a FIFO to decouple output and input. 4 Bit, or 32 Bit, as long as possible.
We use simple crystals with switching between 22.5792/24.576MHz and add literally Micha "Brutalsky" Firer style totally brutal pull capacitors so we can let the crystal run as fast as possible (no caps), at nominal speed (nominal load) and al the slowest speed (maximum pull load). I think we can get at least +/50ppm pull range probably more.
We can do all that using RF relays, including improvised UB2/G6K wrapped in self adhesive copper foil. I just want to use "chunky stuff".
So now we have a low phase noise, precision oscillator we can trim digitally 50ppm fast or slow.
We get our CPLD/FPGA FIFO to give the HF (Half Full) and AF/AE flags (normally 1/4 or 3/4 point). Let's also have a 44.1/48 flag.
We start with default 44.1kHz base clock. We count the MCK cycles per WCK.
If it is an even multiple of 16 we keep the set clock, if it is less we step down the clock (unless we are at minimum) otherwise we step up one gear.
We have time to do that because we need to fill the FIFO.
At HF we start the output on our X-Tal MCK divided down, nominal clock load for "center" of clock.
Once we hit AF/AE we compare the HF flag to determine if we are AE (output clock to fast) or AF (output clock t slow).
If we are too slow, we trim our clock to "fast", else to "slow". Yes, each time we make a trim step, the output has a HUGE measured "jitter" but actually, it's just a clock trim, where over tens of milliseconds the oscillator will shift to the new frequency.
If our Fifo management cannot follow our source clock well enough, we switch local MCK off and use source MCK as lower quality but reliable fallback (more relays). In this case the FIFO & IIS2SIM section can also be omitted and jumpered out, for those with JLsounds USB, WM8805 SPDIF whatever...
I think this makes a great all in one TDA1541 PCB for 2025.
Thor
What I was thinking is to add such mode to my USB<->I2S project, it is not going to be hard to do. I already have mode for NOS DAC (or PCM mode) output, I just need to add special case for 16BCLK/Sample instead of 32. And then it would allow direct connection to TDA1541.
For the board like @raptorlightning proposed I'm afraid it would not make much sense money-wise. I'd say it will be better to order the PCB and stencil for manual assembly. Anyways, it is easy to check by uploading gerbers and BOM to jlcpcb website.
Only for people who stock solder paster, cleaner SMD have a hot plate plus hot air SMD rework setup.
Everyone else who needs a single PCB will happily pay a premium, moreso if it's embedded on the PCB that needs SMD fabing at the PCBA anyway.
Thor
True. I can do that if there will be demand for group buy. The only thing I'm missing is the programmer for lattice FPGA.