ADCs and DACs for audio instrumentation applications

[IVX]

May I review one?

And yes - either show the schemas or go -> commercial section...

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the schematic is pretty much the same as shown above, only for a single chip, and FDA input, + switchable input resistors. Of course, I do not go to use "special" $4 LDO from ESS when I can take opa1612 and get less noise. Also, I using CT7601 USB UAC2 because of cheaper and less current draw.
Regarding a review, do you have a decent equipment to evaluate my ADC performance yet?
PS: to be honest, I probably will stop that project at all because I see near to zero interest of potential users to that. This is my personal mania to make something WOW without any market demand will make me a beggar. My portable DACs selling well, I need to be focused on it.

 

[peufeu]

amirm at audiosciencereview will probably be interested in measuring it, that'll give you free publicity.

You could sell just the USB bridge, maybe there is demand for a bridge that works and isn't a XMOS power hog, with an EMI-friendly design?

 

[5th element]

There will definitely be a demand for the ADC with the level of performance you've posted in this thread. I mean the Q401/402 are very popular and this ADC is an order of magnitude better all you need is the publicity and audiosciencereview will do that for you. Just make sure you get it tested at 96/192kHz as well.

 

[Tfive]

the schematic is pretty much the same as shown above, only for a single chip, and FDA input, + switchable input resistors. Of course, I do not go to use "special" $4 LDO from ESS when I can take opa1612 and get less noise.

Let's see if you have proper DIY spirit and tell us more about your OPA1612 implementation...

What caps do you use at it's output? Do you use 100% straight NFB and how did you ensure enough phase margin/stability? By experiment or by simulation?

 

[phofman]

Comments are welcomed, I am in particular interested in ideas for loop testing, before integrating with the XMOS controller and USB bridge.

I am testing ES DAC (+ the coming ADC) with RPi4 I2S in slave mode, runs OK as a hat up to i2s bclk 768kHz/24bit (128Fs 98MHz MCLK for the ES DAC). 768kHz/32bit (49MHz) is already too fast. IMO a simple adapter from the GPIO header to your coax data cables would suffice.

RPi4 has a standard GUI and REW runs on it OK with bitperfect output/input. Takes a bit of configuring linux and simple recompiling kernel for samplerates > 192kHz.

 

[TNT]

Then...

Haha - one of my absolute favourites...

//

 

[staccatiss]

May I invest in the design? To increase your DIY audio budget and later on purchase unit.

Here are the schematics for the ES9822PRO ADC. It is dual mono, however the data sheet is unclear on how to set up multiplexing left/righ data on the same output. I had to make some assumptions and added switching bridges (resistors) to allow several possible combinations. Trial and error will follow...

The input stage use the OPA1612 opamp, not much to comment about.

The power supply, I decided to use the ES9311 LDO regulators for the Reference voltages. The ES9822PRO data sheet is also unclear about the performance required in the AVCC power supplies, so I decided to assume the worse and throw in a pair of extra LT3045 (probably an overkill). Power sequencing is per the ES9822PRO data sheet.

Also attached is the clock generator for the integration with the XMOS chip (software is in development). Pretty much the XMOS audio reference board implementation, with a few tweaks (added clock buffers and series resistors for clock distribution, used a decent clock chip instead of a simple crystal, modified the power distribution).

Unfortunately my Rohde UPD supports only the digital generator as a Master and the digital analyzer as a Slave. There are LRCK I/O BNCs on the back panel, but using those to recover the master clock would require an external ASRC. It would be great if the ES9038PRO DAC (in slave mode) could output the reconstructed x128 SR internal clock, to use it for clocking the (also in slave mode) ADC, unfortunately it doesn't. Or if the Rohde UPD would output the Master clock from the digital output, to be able to drive in sync both the DAC, the ADC and the Slave digital analyzer, unfortunately it also doesn't. So the only way I see possible to test the setup of the ADC and DAC at all SRs is to use the clock generator to drive the ADC and the DAC D_PLL in async mode.

After the XMOS board will be completed (hardware and software still in development) this will not be an issue, because both the DAC and the ADC will work in Slave mode.

Some parts may still have incorrect values, due to the heavy copy/paste when drawing, sorry about. Comments are welcomed, I am in particular interested in ideas for loop testing, before integrating with the XMOS controller and USB bridge.

 

[staccatiss]

I agree!

Also, look at the Danish ADC/DAC instrument from soekris. It costs >1000USD and sells.

There will definitely be a demand for the ADC with the level of performance you've posted in this thread. I mean the Q401/402 are very popular and this ADC is an order of magnitude better all you need is the publicity and audiosciencereview will do that for you. Just make sure you get it tested at 96/192kHz as well.

 

[peufeu]

Combining DAC/ADC in the same instrument allows to synchronize them to the same sample clock, which makes the combo much more useful.

 

[IVX]

I afraid Amir's tests. Last time he did measure my USB DAC dongle with unbalanced 3.5mm jack with unbalanced BNC AP's inputs i.e. he did measure the noise between his PC and AP instead of my DAC. An AP analyzer is a quite stupid device and requires some basic knowledge to be used correctly. I hope Goldensound is the smarter guy and he 3 days ago got APx555 for reviews as well, so I gonna send Cosmos there.
Regarding the "super regulator" I used recommended by ESS way, please take a look ESS 9038Q2M demoboard.pdf

 

[Tfive]

So no bypass caps on the outputs of the opamps / AVCC inputs of the ADC at all?

 

[IVX]

ESS uses no caps, see attached. I do because my 2 layers PCB impedance isn't so low

 

[HpW]

Combining DAC/ADC in the same instrument allows to synchronize them to the same sample clock, which makes the combo much more useful.

in some cases OK, for independent jitter test to avoid. Also to have a modular system as exchange to any better.. see QA401 performance or RTX performance

More important to isolate the USB or using expensive INTONA gear.

ADC to USB up to xxxkHz is still rare... dyhk has a 384khz I2S but do not know the performance, as master only possible or slave as required with required clock..

interesting about akm (decimation) or/ and ESS jitter performance... as ESS dac all converted to dsd even pcm..

 

[Tfive]

ESS uses no caps, see attached. I do because my 2 layers PCB impedance isn't so low

Well then, which values/types do you use?

 

[IVX]

Tweak9822.exe app for Windows in progress. Also working on Cosmos_FFT.exe, which will be pretty plain 2ch FFT app(WASAPI) but with correct THD, THD+N and SNR calculating + a few "new" ideas one is "photoshop" used APx555 to mix before+after notch FFTs to single one. Maybe with generator but I not sure if we need that, rather Tweak9822.exe will be a part of FFT.exe.

 

[IVX]

Well then, which values/types do you use?

10u X5R

 

[altor]

Combining DAC/ADC in the same instrument allows to synchronize them to the same sample clock, which makes the combo much more useful.

Is is also relevant if the DAC is in Async.Mode? (which as I know, IVX always use)

Regarding the "super regulator" I used recommended by ESS way, please take a look ESS 9038Q2M demoboard.pdf

Why U3 is powered also with VS-?

I used similar power supply in many devices, but w/o the negative rail. This decrease OP heating, especially when it power something voracious, like 9038Pro or 4499.

 

[IVX]

I have no idea, it is ESS demoboard, not mine

 

[peufeu]

Is is also relevant if the DAC is in Async.Mode? (which as I know, IVX always use)

It's more about the measurements than about the DAC/ADC.

Sometimes it is very useful when one period of test signal makes an integer number of samples so everything lines up. If ADC and DAC use different clocks, it will not line up, and it will drift.

 

[kn0ppers]

An AP analyzer is a quite stupid device and requires some basic knowledge to be used correctly.

Should have probably sent one of the samples to Tom Christiansen and paid him for testing, he is more qualified than Amir and Goldensound combined imo.