Both actually. Typically the isolation happens after the USB interface at the I2S stage. I'm advocating for adding an extra isolated power supply and clock/data link so there is no galvanic connection between the analog side of ADC and DAC.
I tried to do this a few year ago.
The main problem was a delay (bclk-sd) in the isolation at Fs>=384.
oh, you know this one is the topic which excites me to talk about it for hours
AP is like spiderman to me - cool, expensive, a legend but actually weak and archaic first, 10x overpriced next. For instance, AP always limits the BW in the last stage, and due to >1MHz max BW their frontend is very easy to overload with a tiny amount of a HF noise. I remember how Amir did argue me kinda he don't care about the HF noise at all because he turned On AP's 22kHz BW limit. One more I hate in AP, it is unreliable. I had maybe 20pcs SYS27** on my previous job, and I remember we always had something wrong with APs. We did send APs to repair for $1500 at least, even when AP needs only recover the EEPROM content. If EEPROM every year losing its data, it is not a user problem at all(actually, I believe the root cause was a poor "analog style" PCB layout).
Regarding the "legendary performance" is also a myth, my AP SYS2522 is noisy but less noisy than APx555 released 20 years later for $30000. When I switch an input impedance of AP for 300 or 600ohms I think - why not reduce a few resistors together to keep residual noise lower than .8uV? Just a few relays more and $30000 analyzer will be able to measure the noise of a cheap Cirrus CS43131 DAC(residual noise 550nVrms A-w), why not?? The same thing with THD+N, APx555 with -123-125db is way worse than modern DACs can show.
Everyone here can make for a couple of hours 1khz notch with a few res/caps and reliably overtake APx555, I think it is a shame.
In case something like this was made, how much isolation do we need?
1. Would it be sufficient to isolate the outputs from the inputs, so with inputs still "connected" to the safety earth?
2. Assuming there are two outputs, do these have to be isolated from each other or could they be galvanically connected, as long as they are isolated from the ADC side (and the USB of course)?
I realize that the lack of isolation is a shortcoming of the RTX6001 (as you have also pointed out previously). The ground loops would be less of a problem with isolation at one end of the signal chain. But if we want to keep it (relatively) simple, how much isolation would be sufficient?
I using Hifi.me USB2 isolator $100 with AP USB interface because AP has no isolation or have but a bad one. At least Hif.me isolator with replaced 5000pF Y cap for the 50pF can work a few minutes and noticeably improves measurements related to my PC GND. There is some rare ISO SO16 chip Silana ICEUSB3 works with Ti USB HUB chip used like a buffer as I see. I asked Silana about that IC but they said it was discontinued forever and they never back with a replacement.. I hope they sold the design to somebody bigger where we'll be able to buy a similar ISO chip, probably reliable functional with 50pF.
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Is this full speed or high speed? Looking at the board, I would say it's full speed only (meaning up to 96k audio), high speed isolators are using extra logic (like FPGAs) to help negotiating the speed and direction between the two halves and, as a result, are much more expensive.
For full speed there are plenty of solutions, probably the most common one is the ADUM4160 ADUM4160 - Advice re schematic - Q&A - Interface and Isolation - EngineerZone
For full speed there are plenty of solutions, probably the most common one is the ADUM4160 ADUM4160 - Advice re schematic - Q&A - Interface and Isolation - EngineerZone
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If you want it done right you'll probably have to do it yourself after the USB. More work, but it can be done better. In torture testing we did on a medical device we found we could not use ADuM4160 in the design. It met all specs in terms of isolation but it made USB more prone to reset in case of ESD and EMI susceptibility testing at levels beyond the standards usually go. That's if you could accept the Full Speed limitation anyway.
Thanks, I guess it would be much more effective to isolate only the ADC and DAC using standard high speed isolators (like I suppose Jen did), and leave all the XMOS s*it on the USB side. Clock switching and jitter cleaning would also be on the ADC/DAC side The XMOS evaluation board does not consider any of these isolation issues, so it will be quite some re-design.
Virtins has a high speed USB isolator (available at DigiKey) but it is, of course, expensive https://www.virtins.com/VT-USB-ISO-480.pdf
Virtins has a high speed USB isolator (available at DigiKey) but it is, of course, expensive https://www.virtins.com/VT-USB-ISO-480.pdf
