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Thanks Demian,
Interesting observations. BTW, a long time ago when I did my THD analyzer I looked carefully for the best JFETs to use, and learned that JFETs with high threshold voltage and low Rds-on were the winners. I ended up choosing the 4091, which was even better than the 4391. I have not tried lately, but have been under the impression that for quite some time the 4091's are or have been more difficult to find than the 4391's. There is some overlap in the specs between the two, so some batches of 4391's may be as good as 4091's.
A key concern that I often have is that, while reducing the signal voltage across the JFET significantly reduces distortion that it may introduce, that reduction can end up increasing the oscillator noise by increasing the amount of noise injected into the oscillator by the agc correction signal for a given amount of available agc control range. It is critical that any amplifying circuitry following the JFET in the path to injection into the oscillator loop have very low noise. This fits in with the desire to have the JFET operating at a relatively low value of resistance.
This is where a fixed-frequency oscillator that is optimized for just that frequency has a big advantage. For one thing, the components can be optimized and precise for that one frequency, significantly reducing the amount of agc range needed. An oscillator that must cover a decade generally will need significantly more agc range because needed agc correction can be frequency dependent for many reasons.
Cheers,
Bob
Granted that distortion may worsen, but the incentive is to to have a drift-free oscillator, preferably synchronized to a FFT bin, to facilitate lengthy averaging and noise floor reduction. This notion seems to be a recurring wish in this thread.
In earlier posts Victor indicated that his oscillator distortion was not dominated by ALC distortion, but rather other subtle mechanisms. It is hoped that VCO tuning distortion will also be negligible relative to other phenomena.
That's also true with the injection locking syncing that has been described in this thread (I presume the sync signal itself is a sine of as low distortion as practical). As BSST said, the hope is that one of these methods can lock the oscillator to a quartz-stable source with as little increase in distortion as possible.
Here was the simplest method suggested. I got excellent results using the two op-amp (no common-mode) version of the Christmas light oscillator. Don't know if this can work here.
Injection-Lock a Wien-Bridge Oscillator | Analog Devices
Probably these optocouplers are enough for to control the frequency and also the gain. No need to use the FET else. Proportion between the optocouplers can control the gain. Two control channels for optocouplers are needed - for the frequency and for the gain.
Vic.
AP recognized the issue and solved it in software. My 2722 has that function but the newer models seem to have lost it. Instead of moving the hardware oscillator to 'bin center' it moves the samples to fall in bin centers, allowing high resolution windowless FFT. Anyone with some proficiency in say MathLab or Octave should find this a trivial exercise ;-)
Jan
None, move to bin center
This choice also does not apply a window function, but it is not restricted to signals that are synchronous. None, move to bin center may be used with any signal which consists only of a single sine wave and any harmonically-related distortion products. For signals that are non-synchronous, this selection modifies the signal so that it becomes synchronous.
None, move to bin center shifts the fundamental frequency of the signal to the center of the nearest bin, which is the same as stretching or compressing the waveform so that an integer number of cycles fits exactly in the transform length.
When used with a single sine wave, this technique results in excellent selectivity, with the signal spreading to the adjacent FFT bin normally 120 dB down or more. Due to the correction, the signal in the DSP buffer will now be at an exact bin center and NOT at the original frequency.
Here’s an example: assume that you want to test an ADC operating at a 48.00 kHz sample rate, using a test signal frequency of 997 Hz. This frequency is often chosen because it is non-synchronous with the sample rate and causes the converter under test to be exercised through a large number of its possible states.
With an FFT length of 16,384 samples, the two nearest synchronous frequencies are 996.09375 Hz (exactly 340 cycles in the buffer) and 999.0234375 Hz (exactly 341 cycles). The None, move to bin center mode of the FFT program will shift the frequency of the acquired 997 Hz signal in DSP memory down to 996.09375 Hz (the nearest synchronous frequency) and then perform a windowless FFT.
The result: the ADC under test was exercised at 997 Hz, as desired; and the frequency correction yielded an unwindowed FFT with high selectivity, as if the signal had been at the synchronous frequency of 996.09375 Hz.
The frequency correction technique has a maximum correction range of ±4%. At the low end of the frequency range there will be frequencies that are more than 4% from a bin center. For example, with a 16,384-sample transform and 48 kHz rate, 37 Hz is approximately the lower limit above which a sine wave at any arbitrary frequency can be guaranteed to be brought to a synchronous frequency.
Jan
None, move to bin center
This choice also does not apply a window function, but it is not restricted to signals that are synchronous. None, move to bin center may be used with any signal which consists only of a single sine wave and any harmonically-related distortion products. For signals that are non-synchronous, this selection modifies the signal so that it becomes synchronous.
None, move to bin center shifts the fundamental frequency of the signal to the center of the nearest bin, which is the same as stretching or compressing the waveform so that an integer number of cycles fits exactly in the transform length.
When used with a single sine wave, this technique results in excellent selectivity, with the signal spreading to the adjacent FFT bin normally 120 dB down or more. Due to the correction, the signal in the DSP buffer will now be at an exact bin center and NOT at the original frequency.
Here’s an example: assume that you want to test an ADC operating at a 48.00 kHz sample rate, using a test signal frequency of 997 Hz. This frequency is often chosen because it is non-synchronous with the sample rate and causes the converter under test to be exercised through a large number of its possible states.
With an FFT length of 16,384 samples, the two nearest synchronous frequencies are 996.09375 Hz (exactly 340 cycles in the buffer) and 999.0234375 Hz (exactly 341 cycles). The None, move to bin center mode of the FFT program will shift the frequency of the acquired 997 Hz signal in DSP memory down to 996.09375 Hz (the nearest synchronous frequency) and then perform a windowless FFT.
The result: the ADC under test was exercised at 997 Hz, as desired; and the frequency correction yielded an unwindowed FFT with high selectivity, as if the signal had been at the synchronous frequency of 996.09375 Hz.
The frequency correction technique has a maximum correction range of ±4%. At the low end of the frequency range there will be frequencies that are more than 4% from a bin center. For example, with a 16,384-sample transform and 48 kHz rate, 37 Hz is approximately the lower limit above which a sine wave at any arbitrary frequency can be guaranteed to be brought to a synchronous frequency.
Isn't this just a software SRC? For long averages the temporal drift still matters.
Having assembled a reasonable test fixture I went on to sort through the 100 J108's i got from eBay. I switched to the Shibasoku for this since its fast and has a very low floor with 50 mV in in the test configuration. The fets raged from .004% HD2 to .008% HD2 with a Vdrop of 45 to 60 mV. The HD seemed to have a bigger variation. This batch of Jfets were National. The showstoper was the Siliconix Fets with .024% HD2 under the same circumstances. I was not expecting that. It suggests I'll need to test semis with the same specs for this. Maybe I'll need to get another 100 J108's.
I wander, if someone has measured low price analog switches like CD4066 in similar condition, at the "virtual ground" in inverting or integrator OPA configuration?
The devil must really be enjoying his ice skates! (Semi inside joke.)
I have been running more resistor distortion tests and one option is to lock the FFT to the signal source. It takes a bit for the label acquiring signal lock to go away and the measurement to begin. Not sure how stable it stays for all the 1024 measurements as I see the test signal leakage increase in level with changes in test frequency. I am using the AP system 2 internal signal source.
All the resistors match to better than 1 part in 1,000 so even at low test voltages I am able to look below -160 dB.
All this is after three days of warm up in my office. Might just need to turn off the room's set back thermostat.
Not sure why in doing this type of measurement you wouldn't use the same clock for the DAC and A/D? Why add problems, I thought we were talking about devices unavoidably on independent clocks?
I would have thought the AP uses the same clock, but the results don't seem to show that.
There must be a reason, I have several soundcards that work perfectly with ARTA to do synchronous FFT's.
AP does use the term 'open loop measurement' in their documentation, but that means in their parlance using an external oscillator instead of the internal one.
And, as noted before, the 'no window, move to bin center' software resampling takes care of the external oscillator frequency uncertainty.
Jan
And, as noted before, the 'no window, move to bin center' software resampling takes care of the external oscillator frequency uncertainty.
Jan
Am I correct... the problem is drift in notch and freq?
PLL should take care of that.
David's variable freq. gen seems quite stable when measuring it's -145dbv distortion.
Again... anyone have his schematic? Who handled his estate?
I'd like to try a few opamps Victor uses in David's.
THx-RNMarsh
PLL should take care of that.
David's variable freq. gen seems quite stable when measuring it's -145dbv distortion.
Again... anyone have his schematic? Who handled his estate?
I'd like to try a few opamps Victor uses in David's.
THx-RNMarsh
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David is gone?! Damn. What age, etc?
I had a PM exchange with him a few months ago in which he sent me 4 or 5 schematics. If you think they'd be useful, I think I can track them down.
Regards,
Steve