DAC AD1862: Almost THT, I2S input, NOS, R-2R

@BRN shift registers are good if you are planning to connect it with another I2S sources (like optical to I2S) ... if you stick only with USB jlsounds, then you can connect it directly

Do you know the configuration? It is:
1. PCM1704 like protocols on board oscillators
J2 - Open, J3 - Open, J4 - Close, B1 - Open, B2 - Open, B3 - Open, B5 - Open
connect H1.3 to H1.1 through external 4k7 resistor
Choose required power supply option (page 3 in datasheet v3).
 
Yes, the 4k7 resistor is there.
I just checked the application note for AD1862. It seems BCK should be 17MHz and LRCK 352.8 kHz. If this is correct, that would mean my jlsounds does not provide proper clock signals. Anyone can comment on those freqences please? Thanks.

Guys, is it true about frequencies? If I use BeagleBone Pure firmware + reclocker with oscillators 49.152 MHz \ 45.1584 MHz or 24.576 MHz \ 22.5792 MHz, but this DAC will not work in such a bundle?
 
It all depends how it is connected ;)

For a device with standard I2S protocol the shift registers must be installed (USB to I2S, optical to I2S and all different inputs with standard I2S output).
17MHz is maximum for BCK. Standard I2S word length has 64 Bits (64 BCK cycles).

Simple calculations for different sample frequencies (LRCK):
48 kHz = 64x48000 = BCK is 3.072 MHz (playable)
96 kHz = 64x96000 = BCK is 6.144 MHz (playable)
192 kHz = 64x192000 = BCK is 12.288 MHz (playable)
384 kHz = 64x384000 = BCK is 24.576 MHz (not playable, it exceeded the maximum BCK 17 MHz)
44.1 kHz = 64x44100 = BCK is 2.8224 MHz (playable)
88.2 kHz = 64x88200 = BCK is 5.6448 MHz (playable)
176.4 kHz = 64x176400 = BCK is 11.2896 MHz (playable)
352.8 kHz = 64x352800 = BCK is 22.5792 MHz (not playable, it exceeded the maximum BCK 17 MHz)

One word length (64 BCK cycles = LRCK) contains both channels in standard I2S.
If shift registers are bypassed (with jlsounds or another devices capable to run the AD1862 directly (reclocker configured to drive AD1862 directly)), higher frequencies are possible.
Now let it be little crazy for a special reclocker (probably non-existent) capable to drive AD1862 up to its limit :crazy:
768 kHz = 20x768000 = BCK is 15.36 MHz (is less than 17 MHz, thus playable). But there are not 20-Bit/768kHz recordings, so maximum 24-Bit/705.6kHz or 16-Bit/768kHz recordings are possible with AD1862 on a proper reclocker (IDK how much kHz can be played on jlsounds directly, someone can test it).

AD1862 with shift registers (for almost any I2S source) can safely handle 16-Bit/192kHz or 24-Bit/192kHz :mafioso:
Some I2S devices can shorten the standard 64-Bit word to less common 48-Bit for higher frequencies and make the shift registers non-functional, RPI? #1272
 
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@miro1360,

Any possibilities to create a stackable AD1862 dac? Nowadays, it seems that paralleling / stacking dac chips is preferred for a more analog sound, eg. DDDAC1794, topping D30 pro and etc.

Diyinhk has a stacked option for its ad1862 dac. It would be nice to see such an option become available with your ad1862 dac too.

Thank you.
 
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Joined 2019
a lot of HF pcb engineers are also saying multiplying and stack vertically dac chips is a very bad idea. For instance John from ECDESIGNS made measurements by stacking TDA1541/43 and it increases jitter due to the factory unconcistency of dac chip production. So in a sense, more digital equal not more analog ;)

The goal is to decrease the curent to voltage distorsion by decreasing the resistor value. But it depends a lot of the analog stage too when it comes to talk about "analog" sound here: amount and distorsion spectra : H2, H3, ... Distorsion amount is not all and just a raw data. And here, thanks to the testimonies of users here, for instance Fran than benchmarked a lot here (see link in the well up to date first page of this thread)

From my little experience it also depends a lot of the digital front end and the whole quality of thr power supplies of your dac device as the wireing: typo of supply, type of traffo, streaming quality and chips too (spidf being less good than usb and so on...), crystals quality, buffer, ground isolation, ....


You can notice it's not that easy when you have a chip per channel in a dac to make a good pcb too. Stacking is increasing the complexity here. At the end it might be a not so good trade off, ask perhaps more layers. But who knows, Miro1360 is drawing fast :D.

Your best chance if you don't find ut analog enough is to play with the analog stage and power supplies and also capacitors models at the near decoupling. And between EUVL discrete, opa861 with no feedback, good modern oap too of the list with the adaptators gerber given by cool member of this thread, not talking about tubes, you have more ways to voice your DAC than multiplying an already good dac chip that is rare and expensive. And vertically building is also called an antena in RF HF area if I understood what the engineers said here in DIYA ?! = not good !

IMHO, YMMV of course. And DIYhink makes not so good pcbs imo, btw Miro begun his AD1862 journey with one of their pcb and was not happy enough hence all his good work here :) :lifesavr: !
 
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Yes, the 4k7 resistor is there.
I just checked the application note for AD1862. It seems BCK should be 17MHz and LRCK 352.8 kHz. If this is correct, that would mean my jlsounds does not provide proper clock signals. Anyone can comment on those freqences please? Thanks.

It all depends how it is connected ;)

For a device with standard I2S protocol the shift registers must be installed (USB to I2S, optical to I2S and all different inputs with standard I2S output).
17MHz is maximum for BCK. Standard I2S word length has 64 Bits (64 BCK cycles).

Simple calculations for different sample frequencies (LRCK):
48 kHz = 64x48000 = BCK is 3.072 MHz (playable)
96 kHz = 64x96000 = BCK is 6.144 MHz (playable)
192 kHz = 64x192000 = BCK is 12.288 MHz (playable)
384 kHz = 64x384000 = BCK is 24.576 MHz (not playable, it exceeded the maximum BCK 17 MHz)
44.1 kHz = 64x44100 = BCK is 2.8224 MHz (playable)
88.2 kHz = 64x88200 = BCK is 5.6448 MHz (playable)
176.4 kHz = 64x176400 = BCK is 11.2896 MHz (playable)
352.8 kHz = 64x352800 = BCK is 22.5792 MHz (not playable, it exceeded the maximum BCK 17 MHz)

One word length (64 BCK cycles = LRCK) contains both channels in standard I2S.
If shift registers are bypassed (with jlsounds or another devices capable to run the AD1862 directly (reclocker configured to drive AD1862 directly)), higher frequencies are possible.
Now let it be little crazy for a special reclocker (probably non-existent) capable to drive AD1862 up to its limit :crazy:
768 kHz = 20x768000 = BCK is 15.36 MHz (is less than 17 MHz, thus playable). But there are not 20-Bit/768kHz recordings, so maximum 24-Bit/705.6kHz or 16-Bit/768kHz recordings are possible with AD1862 on a proper reclocker (IDK how much kHz can be played on jlsounds directly, someone can test it).

AD1862 with shift registers (for almost any I2S source) can safely handle 16-Bit/192kHz or 24-Bit/192kHz :mafioso:
Some I2S devices can shorten the standard 64-Bit word to less common 48-Bit for higher frequencies and make the shift registers non-functional, RPI? #1272

Miro, thank you for the detailed answer, 16-44.100 is enough for me in most cases. With this mode, everything should work without problems.
 
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in blind test people indeed hear no difference between 192 and 388 upsampling ! Not sure they even hear one between 88 and 176 Khz either !

I'm also agree than a good 16/44 dac is more than enough too, the dac chip is not alone in what you hear at the outputt of the loudspeakers. NOS is good enough, not sure all are able to hear interpolations in reccordings when using NOS Dacs ?! Certainly lesser and lesser at the age is increasing with the natural cut-off of the aging ears.
 
I use mine with 22/24 clocks (reclocking) and it works just fine. Never used beaglebone/pi stuff so can't comment on that.

I recommend, by most reviews this is one of the best sounding endpoints for relatively ridiculous money, in any case clearly better than Rasbery. By the way, not very bad and not cheap Edel is based on BBB.
And another big plus thanks to Miro for remaking the input pads at my request. And now the DAC from the topic can be directly to the PPY reclocker and BBB, without the "snot" of long wires, and this is also + to the sound quality.
 
I use mine with 22/24 clocks (reclocking) and it works just fine. Never used beaglebone/pi stuff so can't comment on that.

you have also the Rpi pcb made by Allo that is quieter than the original Rpi. And with the Allo Kali reclocker you can have for low monney a good enough async front end with modern streaming capabilities.

I have not heard about this, can I have links?
 
@diyiggy,

Thank you for your advice. I've learnt a lot! Didn't know there are so many potential issues with such a design.

But still I wish to hear how a well implemented paralleled dac sounds. It might be challenging and it might not work at all, but it still might be worth exploring / experimenting, right?

I wish to learn what miro thinks about this.

Cheers