Ultra Amplifier with JFET input and Lateral MOSFET out

Today Christmas came early!
I have several projects on the bench, but will eventually build these. If anyone is interrested in building one of these, tell me. I have a few pairs available.

HEXFET version

Ultra_HEXFET_PCB.png


Cascode version with Exicon

Ultra_Cascode_PCB_1920.jpg


Schematics earlier in this thread.

Happy weekend!

🙂 morten
 
Yeah right.

Why sneak in advertisement, it is not appropriate. I did not see anyone stop you from creating your own PCB. You are also welcome to share your skills and allow members to give some feedback on your PCB designs. You may also offer group buys, you can do absolutely anything you want except advertise, there is a Marketplace for this. I did not attack you, I did not even know of your existence until your post to me, but if you feel that I directed an attack on you I am truly very s

Yeah right.

Why sneak in advertisement, it is not appropriate. I did not see anyone stop you from creating your own PCB. You are also welcome to share your skills and allow members to give some feedback on your PCB designs. You may also offer group buys, you can do absolutely anything you want except advertise, there is a Marketplace for this. I did not attack you, I did not even know of your existence until your post to me, but if you feel that I directed an attack on you I am truly very sorry.
Send a PM, please
 
My first test build is coming along...

The two red wires are for a dumb mistake that I made, which caused the rails not go to drivers and IS. The BJT on the twisted wires is the one to prevent thermal runaway (I am trying with RF640 and IRF9640 instead of the Exicon laterals). I used a TTC011B, which did not prevent the bias from rising with heatsink getting warmer. I will need to try others. Anyone having a recommendation of a TO-126 or TO-220 which has a gain like the bC546C?

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Mounted on heatsink. With the transistors being unter the PCB, it was a little intricate to mount them.

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After tweaking resistors in IS and VAS slightly, I could bias pretty well in general, as well as get DC offset to 0.
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Despite the fact that in the current state there is thermal runaway happening, due to the size of the heatsink, this is going slowly enough so that I will be able to run some signal through the amp, likely tomorrow or on the weekend.
 
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Where are you mounting the sensing transistor? Try putting it on top of one of the output devices. That will come closets to reading the junction temp of the MOSFETs. If it's between them on the heatsink, it probably got too much thermal lag (if that's the right phrasing).
 
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A question to you gurus: In principle (and besides the not yet solved thermal runaway), the amp is working with the vertical MOSFETs. There is an issue with the zero crossing though. I have tested with 1mA and 2mA IS bias current. No change. Power MOSFET bias is 500-600mA.

What might be causing this? Any advice?

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What current are you running the VAS at? I'm far from a expert on Vertical MOSFETs in Class AB but I recall reading that they benefit from a lot of gate current to drive their capacitance. Maybe this is what's going on? I think Bob Cordell's MOSFET with Error Correction runs at 40 to 50 mA of drive current. That's a tall order in a design without drivers.
 
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OK, I would say it is definitely a result of me trying to run the IS with too low bias current. I will change tomorrow (I suspect my attempt to run at 2mA earlier was somehow flawed).

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And the cause is that the voltage on the drains of the Fets, which is feeding the VAS, is not sine but completely garbled in that case.

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This is how the gate voltage looks like for the power MOSFETs 😆 .

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@lineup, when analyzing the issues described above, I noticed something else: The IS output with VAS transistors connected is not at all the original wave form. With the NFB the amp has, this is not showing on the output, but isn't this still pretty non-ideal?
With a sawtooth signal, this very easy to see. Also, frequency response and phase on the IS output looks bad to me.

Your latest schematic had J113 and J176, but this happens identically in that and those using the LSK/LSJ from the beginning.

The IS output waveform is not distorted if I just put a 10k resistive load on the IS output.

This somehow makes me think the IS overloaded by the VAS?

lineup-ultra-is-overloaded.jpeg
 
Distortion drops a bit when the IPS/VAS run at a higher voltage. But the main reason (IMHO) is to improve PSRR and reduce dissipation in the MOSFETs when running a high bias. Since MOSFETs don't suffer from GM doubling like BJTs, you can feed them as much bias as your heatsinks can handle, increasing the Class A region.

By using elevated IPS-VAS rails the MOSFETs can swing closer to the rails, providing more output potential without increasing the rail voltage the MOSFETs are running on. This in turn results in lower dissipation. For example, elevating the rails by 6V should provide around 3V more of swing to the MOSFETS.

600mA of bias with 30V rails = 18W dissipation = 5.76W Class A into 8R
550mA of bias with 33V rails = 18W dissipation = 4.84W Class A into 8R

30V main rails and 36V IPS-VAS rails should provide approximately the same Class AB output potential as everything running at 33V.

Another benefit is that boosting the rails allows for filters on the IPS-VAS rails to improve PSRR without reducing output potential.