Ultra Amplifier with JFET input and Lateral MOSFET out

Thank yoy, chermann!

It was me, not chermann 🙂

Any thoughts about using the TL431

Not sure what you mean regarding the TL431. I suppose you used that somehow in the power supply? That will not be related to what I pointed to.
See next post.

Lineup does not build. He "only" designs in simulation. So if he proposed a vertical variant (I actually do not remember that, I described my attempt of using verticals in this thread).
Thermal runaway will not be seen in the simulation.

When starting to test with the MOSFETs in place, use power supply with current limitation and carefully watch the bias current during the amps heat-up. Current limiting will prevent you from frying the output MOSFETs.

If you see the bias rising and rising, even if setting it to a pretty low value when the amp is cold, that is thermal runaway. I would be surprised if you were not seeing it, but I am looking forward to your experience.

If you have it, you might need to get your hands on laterals.
 
I just did a search myself too, hehe. The TL431 occupies the same space as would a bias spread. That is why I thought it could be placed on the heatsink for some regulation.

Ultra JFET_07 IRFP240.jpg
 
The problem of thermal feedback biasing for the vertical MOSFETs has been "solved" by others here. look around for amplifier circuits by Ostripper or Damir that use those MOSFETs and just borrow one of those bias circuits. They've already been tested and known to work well....
 
  • Like
Reactions: m0rten
This works well at least in LTSpice sim. :
 
  • Like
Reactions: m0rten
So, could this be as simple as replacing the TL431 with an IRF840 (will a close cousin be ok? I do have the IRF540, 610 and 630 in the bin)... and maybe increase the resistor values for the bias?
Is it correct to assume that it is the ratio of the gate resistors that is important, not the actual values? I will be running this amp at +/- 24V at the most.
Thank you guys for your advice!

🙂 morten
 
I do actually hope to run this amp in class A. And running in class A is perhaps the reason the HEXPETs behave better? How much quiescent curent do you think I need? My Rs is 0R22, practically the same as in F4. And supply is the same.
 
Quiescent current depends upon how big of a Class A envelope you want. Nelson has many articles on this. It is typically about twice the bias current into the output before the other device shuts off. You might also hit the voltage rails before you hit the current limit. Depends on the load. Practically, you would size the quiescent current based on the size of heatsink you plan to use. I’m sure the real experts here will correct me if I said something wrong.
 
1. Adding degerative resistors, (e.g. 0.22 Ohm), to the source of output mosfets.
2. Create a Vbe multiplier with BJT, mount it on the heat sink near the output mosfets for thermal negative feedback. I never tried with Vbe multipliers with MOSFET as someone mentioned. Not sure how a MOSFET Vbe mulitplier would behave.
3. Big heat sink. In theory, if you have a small enough thermal resistance, you don't need degenerative resistors or thermal feedback.
 
A constant bias generator output will see the output mosfets runaway as they warm up.
The best Vbe multiplier for this role uses a small mosfet, like an IRF510. The bias voltage will reduce as the output stage warms, keeping the quiescent constant, or at least close to constant.
There are other methods for mosfet bias but a TL431 is not the answer.

HD
Thermal time constants may be in the order of many seconds for large heatsinks, but the interesting bottlenecks are inside the device itself.

I can see some interesting effects happening since the 'channel' that gets enhanced is basically sandwiched between the oxide and the "less enhanced" silicon.

Maybe an expert could confirm(?) but it seems that the thermal conductivity of the doped silicon will be highly variable and localised: in the enhanced state the increased electrical conductivity helps it conduct heat, too.

One thing I think happens, is that whenever there is a current peak, the conductive channel momentarily thickens so the temperature gradient across the conducting part is "reset" very quickly to a smooth curve with good linearity. However, as soon as current is reduced, thermal conductivity also drops, so you start getting 'ghosting': like a short-term memory of previous current peaks.

I can see a case for sticking to 100-150mA idle for the Profusion MOSFETs to minimise drift, but I like the 'contrarian' topologies like Le Monstre or Nelson Pass' ACA Mini, or just single-ended, because then feedback can be taken from the source resistors.

Looking at the schematic from page 1, the complementary LTPs are one way to split the signal. Then if it's OK to drive VAS transistors like that, then why not MOSFETs?