As far as I am concerned, there is no advantage in the long-version.
The version I published will fit the usual 100x100mm footprint of PCB shops.
And the design is done such that it does not require 70µm copper.
The design of Twitchie is his own work.
As far as I can see, it does not have provision of DC servo.
It also has much longer copper traces.
And there is no visible increase in MOSFET thermal spacing.
So it is not what I would recommend.
If you must have that, you should contact Twitchie on your own.
And he will have to address any issues with that PCB design.
Patrick
The version I published will fit the usual 100x100mm footprint of PCB shops.
And the design is done such that it does not require 70µm copper.
The design of Twitchie is his own work.
As far as I can see, it does not have provision of DC servo.
It also has much longer copper traces.
And there is no visible increase in MOSFET thermal spacing.
So it is not what I would recommend.
If you must have that, you should contact Twitchie on your own.
And he will have to address any issues with that PCB design.
Patrick
Already explained in the revsion PDF :
https://www.diyaudio.com/forums/att...s-dont-semisouths-udness-revisions-191219-pdf
Patrick
https://www.diyaudio.com/forums/att...s-dont-semisouths-udness-revisions-191219-pdf
Patrick
I just used the balanced connection with a balanced source and all my hum/buzz problems were solved. I do not know exactly what caused the interference in the first place but most probably a ground loop.
I have a thermistor between chassis gnd and PSU gnd as desribed in the Pass CRC PSU schematic for example here: F6 Illustrated Build Guide
Last edited:
After posting results for our speculated DC F_Ate :
First Watt F8
someone asked if a N-JFET + PMOS inversion is possible.
Of course it is, in Spice at least.
You should really use a cascode to reduce the dissipations of the 2SK209GRs.
Alternatively, a single 2SK170BL (~8mA Idss) would do nicely.
Patrick
.
First Watt F8
someone asked if a N-JFET + PMOS inversion is possible.
Of course it is, in Spice at least.
You should really use a cascode to reduce the dissipations of the 2SK209GRs.
Alternatively, a single 2SK170BL (~8mA Idss) would do nicely.
Patrick
.
this seems really GREAT!
Thanks a lot for investigating this Patrick.
I there a way to avoid cascoding with 2sk2145?
Maybe with 3mA Idss and +-15V psu it should be feasible?
25Vx3mA= 75mW 50%from max power margin (150mW)
Or using J113....
why do you use Q2 and D1 for the cascoding bias?
a simpler resistor network wouldn't be sufficient?
Thanks a lot for investigating this Patrick.
I there a way to avoid cascoding with 2sk2145?
Maybe with 3mA Idss and +-15V psu it should be feasible?
25Vx3mA= 75mW 50%from max power margin (150mW)
Or using J113....
why do you use Q2 and D1 for the cascoding bias?
a simpler resistor network wouldn't be sufficient?
Last edited:
After posting results for our speculated DC F_Ate :
First Watt F8
someone asked if a N-JFET + PMOS inversion is possible.
Of course it is, in Spice at least.
You should really use a cascode to reduce the dissipations of the 2SK209GRs.
Alternatively, a single 2SK170BL (~8mA Idss) would do nicely.
Patrick.
Hi Patrick,
A thought occurred to me while thinking about a version with a little more power. One solution is to cascode the input device. But, in spirit of simplicity as Nelson advocate, I came to wonder if one accepts AC coupling, as Nelson's F8, one could arrange the offset voltage and thereby the voltage across the input device so it stays well within the maximum limits could make it possible to avoid cascoding. I assume one could choose a resonable valued feedback resistor to get some voltage drop across it to lower the VDS of the input device.
Do you see any fault in my thinking?
Another matter is of course how many mosfets can be driven with a single input jfet. But that is another story.
Mogens
2SK209 is rated at 50V, 150mW.
In theory you can go up to +/-45V rails, as long as all devices can take the dissipation.
Changing supply rails from +/-50V to single supply of 100V does not change anything in terms of output power.
You only add complication with additional input and output coupling.
The argument for single supply rail is because people want to use cheap SMPS for supply.
But why would you spend money to build Class A and then save money on PSU ?
As to increasing the number of MOSFETs, the Spice files are published.
So you can play with any variations as you wish.
Patrick
In theory you can go up to +/-45V rails, as long as all devices can take the dissipation.
Changing supply rails from +/-50V to single supply of 100V does not change anything in terms of output power.
You only add complication with additional input and output coupling.
The argument for single supply rail is because people want to use cheap SMPS for supply.
But why would you spend money to build Class A and then save money on PSU ?
As to increasing the number of MOSFETs, the Spice files are published.
So you can play with any variations as you wish.
Patrick