What is the ideal method for switching between clocks? RF relays would seem good but the isolation still isn't great... overall might not be any better than a MUX designed for clock distribution? Analog MUXes don't have great isolation. Not sure what you'll achieve with a "digital" one.
I suppose you could power off the other clock or use two relays, but more complexity.
I suppose you could power off the other clock or use two relays, but more complexity.
The TWTMC-D&D daughter board uses an RF relay to switch between the oscillators and one more relay to power off the oscillator not in use.
IMHO RF relay is the best solution although the more expensive. And I would never power off the oscillators.
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The volume of the quartz blank counts. The more (flawless) volume, the better
the Q and the less the crystal is annoyed by its environment. That is why they
use overtone crystals even at 5 MHz for precision oscillators. 3rd overtone
blanks are 3 times as thick, plus the 'inner' parts are not detuned from electrode
metallization etc.
The adjustment range of the frequency gets smaller by the square of the overtone.
5 MHz is a sweet spot for precision crystals in that the crystal impedance does not
get too high, one can still find flawless blanks, the mounting does not need to be
too massive (which would dampen).
The 10 MHz MV-89A oven is in fact a 5 MHz one, with internal doubler. One still
can see the 5 MHz on the spectrum analyzer, only 35 dB or so down. If one needs
good cycle-2-cycle jitter, this must be further suppressed unless you divide the
10 MHz by an even number anyway.
Another drawback is, that the far-out noise rises by 6 dB for every *2.
A solution is to have 2 oscillators, a 5MHz one for good close-in noise, and
a phase-locked-to-the-5-MHz one at, say, 100MHz. Then one gets the good
far-out noise from the non-multiplied 100 MHz osc, and within the PLL
bandwidth the good close-in phasenoise of the 5MHz is transferred.
HP has done that in the generation of the 640 MHz reference frequency
of the 8662A / 8663A of their (then) top-of-the-line frequency synthesizers.
Plus crystal filters, SAWs etc.
The doubler itself is quite harmless. You can use a push-pull doubler with
a ferrite core transformer and 2 Schottky diodes, or JFETs or BJTs.
an example is in
<http://www.hoffmann-hochfrequenz.de/downloads/DoubDist.pdf >
There is more interesting stuff in this directory.
FETs have the drawback that they are all individuals, it is easier to get
good fundamental suppression with BJTs.
regards, Gerhard
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Hello All,Salve Andrea,
I received oscillators, thank you.
I have a question I had to ask there almost a year, I did not know what I was swimming water, so that I ask this question now, in the meantime, I changed my sound card, and I will use these 2 oscillator for my Lynx AES 16.
I use 3 dac in multiamp these dac have a 12.8 MHz oscillator (AT-49) low profile, I have not set list, because I was more or less over, no one would have chosen this frequency not very common, but also in this dac, there is a chip called (exo-3c), and also, an OCXO (fujitsu 18m432 d300) @ + - 1000ppm, the dac, yamaha da2x.
my issue are:
1) do the chip, exo-3c is a reclocker? Because I tried a nkg3001b VCTCXO, instead of the oscillator, at-49, and it is no worse and no better.
2) compared to the first question, is it worth it to put a single oscillator for three dac.
The only measure I can do is the frequency, for the rest, I relied on my ears.
If someone wants to respond, it will remove me a thorn in the foot.
Best Regards,
Stefano
I received oscillators, thank you.
I have a question I had to ask there almost a year, I did not know what I was swimming water, so that I ask this question now, in the meantime, I changed my sound card, and I will use these 2 oscillator for my Lynx AES 16.
I use 3 dac in multiamp these dac have a 12.8 MHz oscillator (AT-49) low profile, I have not set list, because I was more or less over, no one would have chosen this frequency not very common, but also in this dac, there is a chip called (exo-3c), and also, an OCXO (fujitsu 18m432 d300) @ + - 1000ppm, the dac, yamaha da2x.
my issue are:
1) do the chip, exo-3c is a reclocker? Because I tried a nkg3001b VCTCXO, instead of the oscillator, at-49, and it is no worse and no better.
2) compared to the first question, is it worth it to put a single oscillator for three dac.
The only measure I can do is the frequency, for the rest, I relied on my ears.
If someone wants to respond, it will remove me a thorn in the foot.
Best Regards,
Stefano
@Gerhard: Thanks for the clarification ... I see there are some options in terms of multiplying the basic frequency although one has to observe various phenomena by so doing.
Yes, I've noticed - have been reading e.g. your capacitor decoupling experiment & the battery noise measurements - interesting & quite accessible information I think (thanks for providing it ;-) )
@1audio: Thanks also for your comment. Just out of curiosity - would this also mean that HF crystals are more prone to microphony/vibrational disturbances than lower frequency crystals?
Have a good weekend
Jesper
an example is in
<http://www.hoffmann-hochfrequenz.de/...s/DoubDist.pdf >
There is more interesting stuff in this directory.
Yes, I've noticed - have been reading e.g. your capacitor decoupling experiment & the battery noise measurements - interesting & quite accessible information I think (thanks for providing it ;-) )
@1audio: Thanks also for your comment. Just out of curiosity - would this also mean that HF crystals are more prone to microphony/vibrational disturbances than lower frequency crystals?
Have a good weekend
Jesper
Fujitsu 18m432 d300 (certainly not OCXO) is for YSF-210B digital filter. Some Yamaha digital filter can work asynchronously. In your case, a clock for 432fs or more can be used.
Andrea what do you think of these osicllators http://www.diyaudio.com/forums/swap-meet/285369-ultra-low-jitter-generators-22-5792-24-5760-33-8688-36-8640-45-1584-49-1520-mhz.html
@merlin il mago:
Just FYI:
http://www.diyaudio.com/forums/digi...itter-crystal-oscillator-120.html#post4726529
Best regards,
Jesper
Just FYI:
http://www.diyaudio.com/forums/digi...itter-crystal-oscillator-120.html#post4726529
Best regards,
Jesper
Hello canvas,
thank you for answering, it's true, this is a VCO.
My crystal 12.8mhz, does not fit in the ysf 210b, @ 384 x fs (from 11 to 22 MHz), but in the ym3436b, @ 256 x fs (7.37 to 13.5 MHz).
Ok, I think I understand why a quartz 12.8mhz instead of 12.288mhz was used because there is the function "vari pitch".
However, I do not understand that there was no difference in the sound, changing the oscillator.
I did make a high res. pdf, of my service manual, but it is too heavy to post, besides, I do not know if anyone is interested.
Best regards,
Stefano
Hi Stefano,
As I remembered, YM3436 XI is used when PLL is not working/locked. In most situation, it's the internal PLL which supply the clock for functioning or timing purposes.
Hello canvas,
how I interpret what you just told me "it is useless to try to change quartz, as this will not influence?", or something different.
Anyway, it sounds very good as it is, and it can remain as it is.
Trying with VCXO, was to see if the sound could be even more fluid.
Best regards,
Stefano
This is off the topic. I think you may start a new thread for the DAX2.
The 18.2M XO is for MCU, so it has no effect on sound quality. Follow the XI trace of YM3436, you will see another 18Mhz oscillator. IMHO, it's not worth it on fiddle with Yamaha DIR & filter (I tried). The designer knew this and built external PLL for DAX2. The fujitsu multi OX package is the reference clock source for the external PLL.
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Hello All,
although my dac is not diy, in my opinion, it's a little part of the thread.
The initiator of this thread, do not hold me rigor, but trying other noncommercial clock, not as advanced as that of Andrea Mori, the sound improves.
At the risk of making me look like an idiot, now there are 120 pages of theory,
stakeholders are a handful of people, who perfectly mastered the subject, which is very interesting, however quite complicated for non-electronics which I belong, unless wrong, I do not think the only (all those who are not in my case, raises his hand, if any), but when everyone has received his equipment, and follow the instructions given by Andrea in pdf, welding components, at some point, it will still speak of practical application, although there is no obligation to provide assistance, given the diversity of dac, sound card, or cd player.
So, is there going to be a dedicated thread for the implementation of this master clock, and potential application problems, if there are?
Hello canvas,
no problem, I can open a thread,
no,
there are three clock mentioned above, the rest is composed of a miriade of inverter.
If you already have the schematic,no worries if you do not have it, and you're interested, I can send it to you or any other person.
Best regards,
Stefano
although my dac is not diy, in my opinion, it's a little part of the thread.
The initiator of this thread, do not hold me rigor, but trying other noncommercial clock, not as advanced as that of Andrea Mori, the sound improves.
At the risk of making me look like an idiot, now there are 120 pages of theory,
stakeholders are a handful of people, who perfectly mastered the subject, which is very interesting, however quite complicated for non-electronics which I belong, unless wrong, I do not think the only (all those who are not in my case, raises his hand, if any), but when everyone has received his equipment, and follow the instructions given by Andrea in pdf, welding components, at some point, it will still speak of practical application, although there is no obligation to provide assistance, given the diversity of dac, sound card, or cd player.
So, is there going to be a dedicated thread for the implementation of this master clock, and potential application problems, if there are?
Hello canvas,
no problem, I can open a thread,
no,
there are three clock mentioned above, the rest is composed of a miriade of inverter.
If you already have the schematic,no worries if you do not have it, and you're interested, I can send it to you or any other person.
Best regards,
Stefano
Hi all,
... I've been wondering ... Andrea, and more people, have now been involved in designing a superb range of oscillators jitter/phase-noise-wise (to be tested relative to eachother in due time), however, what is the intrinsic jitter in some of the newer ADCs or DACs?
The only IC's I've seen specified are the new SAR ADCs like LTC2378, LTC2380, MAX11905 - but I've never seen any specifications e.g. for the intrinsic jitter of any of the newer DACs. And so, now, a superb oscillator might be combined with a less than optimal DAC ... Any of you are aware if there are DACs with very fine jitter specs - or have been thinking about this?
Cheers,
Jesper
... I've been wondering ... Andrea, and more people, have now been involved in designing a superb range of oscillators jitter/phase-noise-wise (to be tested relative to eachother in due time), however, what is the intrinsic jitter in some of the newer ADCs or DACs?
The only IC's I've seen specified are the new SAR ADCs like LTC2378, LTC2380, MAX11905 - but I've never seen any specifications e.g. for the intrinsic jitter of any of the newer DACs. And so, now, a superb oscillator might be combined with a less than optimal DAC ... Any of you are aware if there are DACs with very fine jitter specs - or have been thinking about this?
Cheers,
Jesper
Its a very legitimate question. And on audio DAC's (and audio ADC's) its not usually specified. Delta Sigma works differently so the spec would not translate directly. However the noise floor of the chip is indirectly related. Higher jitter = higher noise in the presence of signal. Probably the real goal would be to translate jitter/phase noise into equivalent noise in the output of the DAC. This would get involved and best done in units like nV/rtHz. And conversely if the chips noise floor is e.g. -150 dBFS/rtHz then jitter a lot below this won't make a difference.
Its helpful for visualizing whats happening to think of the system like a superhetrodyne receiver with the sample clock as one of the modulating inputs. Without audio there is no modulation and no audio band signal. With modulation you get the audio (and the image on the other side of the sample clock).
Its helpful for visualizing whats happening to think of the system like a superhetrodyne receiver with the sample clock as one of the modulating inputs. Without audio there is no modulation and no audio band signal. With modulation you get the audio (and the image on the other side of the sample clock).
@1audio:
Thanks Demian for the comment and comparison ... I've looked up the superheterodyne amplifier on wikipedia and it's a useful comparison to me in terms of a "complexity" in what happens when a signal is present versus when none is present.
I also remember reading in the "low distortion oscillator thread" and JH's "analyzer thread" that you sometimes have meetings with AK. Any chance you've discussed what their jitter spec targets are when designing their ICs (if you are at liberty of sharing this)? Could be interesting to know.
E.g. Analog Devices in the AD7760 datasheet specifies a max jitter value for a given sampling frequency, e.g. 1.79 ps for a 2.5 MHz sampling frequency, meaning that the ADC itself must be lower than that.
Cheers,
Jesper
Thanks Demian for the comment and comparison ... I've looked up the superheterodyne amplifier on wikipedia and it's a useful comparison to me in terms of a "complexity" in what happens when a signal is present versus when none is present.
I also remember reading in the "low distortion oscillator thread" and JH's "analyzer thread" that you sometimes have meetings with AK. Any chance you've discussed what their jitter spec targets are when designing their ICs (if you are at liberty of sharing this)? Could be interesting to know.
E.g. Analog Devices in the AD7760 datasheet specifies a max jitter value for a given sampling frequency, e.g. 1.79 ps for a 2.5 MHz sampling frequency, meaning that the ADC itself must be lower than that.
Cheers,
Jesper
Earlier in the thread several people were talking about the 74HC04 and wondering why each inverter is actually three inverters in series. This is because of THE basic trade off of CMOS.
For a particular process technology there is a basic transistor size, this transistor has a certain input capacitance and on resistance. The on resistance determines how much current the output can handle.
A single transistor has a pretty high resistance, the way to decrease it is to put transistors in parallel, this lowers the resistance, the more transistors you put in parallel the lower the resistance. But there is a price, the more transistors in parallel, the higher the input capacitance. That capacitance has to be charged by the output of the previous stage. The higher the input capacitance the longer it takes to charge, thus the slower the stage is.
There is no way to get around this with a single stage, if you want more drive, you increase cap, which slows things down.
The 74HC04 gets around this by using a multi-stage device. The first inverter just has a single pair of transistors (N and P channel), the third stage has a lot of transistors in parallel to get good drive and the intermediate stage has some number of transistors in between the first and last stages.
This approach gives you large output drive with small input cap with a reasonable delay through the three stages.
The unbuffered version just has the single stage so its maximum output current is much lower than the three stage version. For a given load driven by the inverter the U04 will have a shallower ramptime (higher resistance) which means the peak current pulled from the power supply will be less, thus less noise on the power and ground planes, which MAY be a factor in the sound quality. BUT the shallower ramptime in and of itself can result in increased jitter at the input it is driving, so it may be worse, it is really hard to tell which is going to be more of an issue.
John S.
For a particular process technology there is a basic transistor size, this transistor has a certain input capacitance and on resistance. The on resistance determines how much current the output can handle.
A single transistor has a pretty high resistance, the way to decrease it is to put transistors in parallel, this lowers the resistance, the more transistors you put in parallel the lower the resistance. But there is a price, the more transistors in parallel, the higher the input capacitance. That capacitance has to be charged by the output of the previous stage. The higher the input capacitance the longer it takes to charge, thus the slower the stage is.
There is no way to get around this with a single stage, if you want more drive, you increase cap, which slows things down.
The 74HC04 gets around this by using a multi-stage device. The first inverter just has a single pair of transistors (N and P channel), the third stage has a lot of transistors in parallel to get good drive and the intermediate stage has some number of transistors in between the first and last stages.
This approach gives you large output drive with small input cap with a reasonable delay through the three stages.
The unbuffered version just has the single stage so its maximum output current is much lower than the three stage version. For a given load driven by the inverter the U04 will have a shallower ramptime (higher resistance) which means the peak current pulled from the power supply will be less, thus less noise on the power and ground planes, which MAY be a factor in the sound quality. BUT the shallower ramptime in and of itself can result in increased jitter at the input it is driving, so it may be worse, it is really hard to tell which is going to be more of an issue.
John S.
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