The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker

Just a comparison between the BCK coming from the FPGA and the BCK after the reclocker.

The phase noise of the BCK signal directly from the FPGA is very poor, while after the recloker it's fine.

It looks like the FIFO Lite with good oscillators will be able to feed at best the DACs which switch on the BCK like the PCM1704, PCM1794 and so on.
 

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Just a comparison between the BCK coming from the FPGA and the BCK after the reclocker.

The phase noise of the BCK signal directly from the FPGA is very poor, while after the recloker it's fine.

It looks like the FIFO Lite with good oscillators will be able to feed at best the DACs which switch on the BCK like the PCM1704, PCM1794 and so on.




YES Andrea,My dac waits for your FIFO:)
 
Just a comparison between the BCK coming from the FPGA and the BCK after the reclocker.



The phase noise of the BCK signal directly from the FPGA is very poor, while after the recloker it's fine.



It looks like the FIFO Lite with good oscillators will be able to feed at best the DACs which switch on the BCK like the PCM1704, PCM1794 and so on.
Someone must learn from this data [emoji28]
 
We have already tested the FIFO Lite with the Sabre DAC in async mode and soon we will test the same DAC in true sync mode.

I have already got Ian's dual mono ESS DAC and the Buffalo 3se.

We believe the best implementation is using the DAC in true sync mode stopping the DPLL inside the DAC, so the most important signal is the master clock.
The reclocker board is not needed.
 
If I may add, I think beyond the clean LRCK another key value proposition is that your device outputs the synchronous PCM signal required by TDA1541A. This eliminates the stand alone pcb from Iancanada or Ryanj. One less component to screw up the data stream. With Ian's solution, you have one FPGA in Fifo creating the signal, then another FPGA in the I2StoPCM that translates it into the signal preferred for the 1541a. In both cases there are power supplies and connectors all points of failure or sound degradation.
 
Latest revision, from left to right:

- TWSAFB-LT Fifo buffer Lite
- TWSAFB-OI optical output interface
- TWSAFB-OIR optical output interface & reclocker

We are testing the software, then we will test several DAC.
 

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Hi Andrea,

Really, an optical output (TWSAFB-OIR optical output interface & reclocker)?

So no worries optical out to a Chord DAC (optical in)?

I delayed my Ian project 6-12 months as I decided on a 12V Intel i9 low latency PC build. I'm looking at what the Taiko Extreme is doing and trying to somewhat emulate, but it has to run on battery. The Extreme uses a dual Xeon WS motherboard, but that's too much of a rabbit hole and I don't want to run on mains.

SGM Extreme Music Server – Taiko Audio

I'm skipping the low power, low CPU endpoint and trying to jump straight into a high CPU build.

Since I have time and flexibility to re-architect my build, if you're doing optical out then I can plan ahead and adjust as I need time to complete my PC build anyways this year.

Cheers
 
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The TWSAFB-OIR is not not really an optical output, it's an optical isolation interface.

All the signals from the FIFO Lite come via copper and also the output connectors provided by the OIR have to be connected to coaxial cables.
Optical interface is very jittery.

The optical isolator are used to isolate the clean part which comes directly from the master clock from the dirty signals coming from the FPGA, to avoid any interference between the two domains.

Finally, the dirty signals are reclocked by the master clock after the isolators.

The TWSAFB-OIR has to be used only with DAC switching on the BCK, like the PCM1704 and the PCM1794.
The other DAC, where the most crucial signals are the LRCK or the MCK, don't need the OIR.
In these case you can use the TWSAFB-OI which isolates from the FPGA but it does not perform the reclock (not needed since the MCK and the LRCK come directly from the clean clock domain).

The DAC Lite does not need any isolation interface.