Copper and steel are two very different metals in terms of how they interact with electromagnetic fields. Copper tends to be reflective, whereas steel is lossy. Copper is better for shielding electric fields and ferrous materials can be better at shielding magnetic fields.
Also steel tends to produce effects that are more more inductive, and in a similar sort of way the presence of copper may be seen as more capacitive (which is related to types of fields they tend to interact most strongly with).
The above is a very simplified explanation. The point I'm trying to make is that copper and steel aren't just two metals either one of which can be used to make an equally good shield. Its considerably more complicated than that.
Also, cavity resonance is mostly only practical at microwave frequencies. Its something not usually involved with audio circuits even when EMI/RFI is taken into account.
In addition, slew rate is a property of a signal, and it is not equivalent to a filter time-constant (say, not equivalent to aa RC time constant causing linear distortion of a signal).
So, its important to first understand quite a bit about electronics and physics before trying to explain to one's self or to others about some of the details of how shielding works (or doesn't work).
Again, its not that simple. Exactly what are we trying to shield from what when it gets down to some detailed level? What is the physics of the situation, the layout, the voltages and currents, the lengths of wires, etc.
If we have a simple question like the one quoted above, we can only give a very rough and possibly wrong answer. That's because we don't know enough about the little details that are specific to a particular design.
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Probably I would describe what happens a little differently. Maybe something more like this: A possibly "deformed" or mis-timed input data pulse is sampled by a D-flip flop at a time determined by the master clock. The master clock then clocks the sampled data (high or low) to the output of a D-flip flop. Thus a new/replacement data pulse is generated by the D-flip flop and master clock.
The new/replacement data pulse is shaped to represent the same digital information as the original data pulse that was sampled. Basically, the new data pulse should look very similar to the original data pulse, except for that the new/replacement data pulse is a little delayed in time as compared to the original pulse.
Also, data pulses in this case are different from clock pulses. Data pulses carry information in their height (or voltage level; either high or low). OTOH, clock pulses carry information in the timing of their edges.
Also, data pulses in this case are different from clock pulses. Data pulses carry information in their height (or voltage level; either high or low). OTOH, clock pulses carry information in the timing of their edges.
So if input data is shape deformed, despite new timing, continues to be shape deformed. I was right is just a demodulation.
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No, I didn't say that.
It depends on the definition of "deformed." Here are the voltage level definitions for LVCMOS logic:
As you can see, for the 3.3v logic we are using there is a range of voltages that are considered high (2.0v to 3.2v), and a range of voltages that are considered low (0.1v to 0.7v). Anything in the valid ranges indicates a 1 or a 0, respectively.
All that matters is if the input pulse voltage levels are in the legal ranges. Then all that matters about the output voltage pulses we create is that they are also within the legal ranges.
For a pulse to be considered distorted, it has to be outside of a legal range except when it is switching from high to low, or from low to high. However, we do not sample voltage levels while they are switching, so that doesn't matter either so long as they switch reasonably fast (in time for us to successfully sample for the legal voltage ranges.
It depends on the definition of "deformed." Here are the voltage level definitions for LVCMOS logic:
As you can see, for the 3.3v logic we are using there is a range of voltages that are considered high (2.0v to 3.2v), and a range of voltages that are considered low (0.1v to 0.7v). Anything in the valid ranges indicates a 1 or a 0, respectively.
All that matters is if the input pulse voltage levels are in the legal ranges. Then all that matters about the output voltage pulses we create is that they are also within the legal ranges.
For a pulse to be considered distorted, it has to be outside of a legal range except when it is switching from high to low, or from low to high. However, we do not sample voltage levels while they are switching, so that doesn't matter either so long as they switch reasonably fast (in time for us to successfully sample for the legal voltage ranges.
I was wrong to not specify about "deformed".
Do not consider the level of the square, but the slope.
The new/replacement square data pulse from d-filp flops, has a new slope with better steepness or just the same old slop of input but only new time sampled?
If no, a steeper data re-shape happen later, in some logics before R?
Do not consider the level of the square, but the slope.
The new/replacement square data pulse from d-filp flops, has a new slope with better steepness or just the same old slop of input but only new time sampled?
If no, a steeper data re-shape happen later, in some logics before R?
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The new pulse edges should be plenty steep enough for the particular logic family to work well.
It can be argued that edges should be fast/steep enough, but not faster/steeper than necessary. For some types of signals edge steepness (we call it risetime), should be very fast. For other types of signals it doesn't matter nearly as much, and faster than necessary may just amount to a source of unnecessary noise.
For a dac, where risetime is most important is probably for MCLK, and or for whatever clock actually clocks the dac output. That's because amplitude noise can be turned into phase noise (jitter) more easily if risetime is too slow. And, for signals where phase noise matters we don't want to risk increasing that type of noise if we can reasonably avoid it.
It can be argued that edges should be fast/steep enough, but not faster/steeper than necessary. For some types of signals edge steepness (we call it risetime), should be very fast. For other types of signals it doesn't matter nearly as much, and faster than necessary may just amount to a source of unnecessary noise.
For a dac, where risetime is most important is probably for MCLK, and or for whatever clock actually clocks the dac output. That's because amplitude noise can be turned into phase noise (jitter) more easily if risetime is too slow. And, for signals where phase noise matters we don't want to risk increasing that type of noise if we can reasonably avoid it.
I agree about clock signals, what about data risetime importance?
It might be all, because here there no working tolerances like voltages tolerance high/low
It might be all, because here there no working tolerances like voltages tolerance high/low
We normally only read the value of data signals after risetime has fully settled. Therefore having very fast risetime is of much less importance for that type of signal.
EDIT: I am becoming concerned that we are spending too much time in this thread discussing very basic digital electronics. Probably many people following the thread find it quite boring. Maybe it would be better for you to PM with questions, and or maybe you could read a book or take a class in basic digital electronics if you want to learn more. That said, we may have briefly touched on a few points not everyone has thought much about. Don't know if anyone else would like to chime in as to whether they think we should take any further questions like this offline?
EDIT: I am becoming concerned that we are spending too much time in this thread discussing very basic digital electronics. Probably many people following the thread find it quite boring. Maybe it would be better for you to PM with questions, and or maybe you could read a book or take a class in basic digital electronics if you want to learn more. That said, we may have briefly touched on a few points not everyone has thought much about. Don't know if anyone else would like to chime in as to whether they think we should take any further questions like this offline?
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Hi,
Has anyone measured Andrea's push pull regulators (PP micro or PP through holes) for the Discrolls boards and squarer ? (PSRR, CMR, output impedance level/bandwith) ?
Thanks
Has anyone measured Andrea's push pull regulators (PP micro or PP through holes) for the Discrolls boards and squarer ? (PSRR, CMR, output impedance level/bandwith) ?
Thanks
Andrea has had an extended illness for some time. He's fighting it, but we don't know how it will turn out.
