That looks great! Have you used it and listened to the result?
What about using something like this:
https://www.onsemi.com/pub/Collateral/MC10EL35-D.PDF
My original project, which has both PCM and DSM, has successfully finished in PCM mode.
Two way DAC(multibit and DSM)from scratch with input options(SDmicro,toslink and IIS)
I'm now playing with DSM mode. I recently have found necessary SNR for music playback isn't so high even in classical one. It can be less than CD(98dB). IMHO, 90dB is enough because music itself has its own noise floor around 80dB. In the situation, if no DAC topology can have 90dB SNR, it can be the most optimum solution. My original one employs 5bit DSM which can offer 110dB SNR but need a little bit complicated adjustment and expensive devices. It's one kind of overkill.
It's possible for my DAC to output DSD(1bit DSM), though conversion is done by DAC chip(AD9117). Replacement with ADN4664 is probably possible with less degradation. The only difficulty is a replacement for xc6slx25(my DAC) in BGA. If I can implement necessary logic into a small FPGA in QFP(xc6slx09), it can be DIY project both in performance and cost.
High-speed devices like 74ACXX have small propagation delay but usually can't get rid of massive ringing, which ends up the degradation of SNR in no DAC topology. An LVDS receiver doesn't have small propagation delay(less ringing), but tpdlh and tpdhl are almost the same, which generally means rise and fall time are also the same. That's why I'm sure it's the best candidate for no DAC. If you adjust propagation delay between tpdlh and tpdhl, you can improve SNR at least 6dB in my memory two or three years ago. I would say an ECL device you posted also must have propagation delay adjustment for better SNR. I don't know how much ringing ECL device has.
For what it's worth, I could get to 97 dB(A) using a four-tap return-to-zero FIRDAC made with 74AHC02 and 74AHC08 devices converting a 27 Mbit/s bitstream:
74AHC02 and 74AHC08 DAC with 97 dB(A) dynamic range
If the signal-to-noise ratio increases with 3 dB per doubling of the number of taps, one should be able to get to around 91 dB(A) with a single return-to-zero DAC made with 74AHC logic. A pitfall may be slow duty cycle variations due to low-frequency noise in the crystal oscillator: this will affect a single-tap return-to-zero DAC while it cancels out in a FIRDAC with an even number of equally weighted taps.
74AHC02 and 74AHC08 DAC with 97 dB(A) dynamic range
If the signal-to-noise ratio increases with 3 dB per doubling of the number of taps, one should be able to get to around 91 dB(A) with a single return-to-zero DAC made with 74AHC logic. A pitfall may be slow duty cycle variations due to low-frequency noise in the crystal oscillator: this will affect a single-tap return-to-zero DAC while it cancels out in a FIRDAC with an even number of equally weighted taps.
Still slow, but the major problem with ecl logic is the small output voltage swing. Cmos achieves 3 volts peak to peak, ecl has around 12 dB less, so you need to amplify it after analog filtering. 12 dB is doable but harmonics do go up.
Doesn't phase noise also get attenuated (around 6 dB) per doubling of taps?
Enrico Rubiola has some nice papers about it e.g.
https://www.google.com/url?sa=t&sou...FjAKegQIAhAB&usg=AOvVaw3rDvowwmYtzvA6X0KNn9-6
Hope the link works..
Nice find! What's your take one jitter specs by having an fpga generate the clock by means of an internal dpll? I agree firdacs or other multibit is the way to go in that case.
Ecl has virtually no ringing because it uses transmission line techniques. It also suffers almost no ground bounce or common mode problems and therefore is excellent in symmetry and fidelity.
Problems are mostly high power needs: 1 flip flop might need 40 to 70 mA, high costs: up to 400 euro's versus a few cents, complex layout: symmetrical/balanced input and output structures needed as well as different or even negative voltage swings or power supplies, needs transmission line pcb's as well as termination because of the faster rise times and often don't come in familiar packages (hard to solder by hand).
Potato Semiconductors are an excellent alternative: they even share oscilloscope screenshots of some of their parts:
Potato Semiconductor / The GHz TTL/ CMOS IO Interface Logic/ Potato IC
Look under "support" for some screendumps.
Those Potato chips looks very interesting. I think I will order some to play with. Thanks
Where to source them from??
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Those Potato chips looks very interesting. I think I will order some to play with. Thanks
Where to source them from??
Ebay, the only official store I know of. They have many types, afaik never the ceramic or dip/dil versions, just the smt's which should be fine;-)
Btw i have no affiliation whatsoever with that company.
FIRDACs can be single bit as well as multibit - that just depends on how many bits each unit DAC has.
A firdac is usually done by serial to parallel conversion. If it's done 1 bit: either I'm missing the point of the conversion from serial to parallel, or I'm completely off here.
What am I missing?
Edit: the point that I was trying to make is that with single bit conversion, which was the leading topic of the last pages, needs a really low jitter clock to succeed and that with multibit the demands are orders lower to get to the same quality. A fir dac has the same advantage (mostly done multibit).
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When you have, for example, eight single-bit DACs driven from a shift register and you add or average their output signals, I would call it an eight-tap single-bit FIRDAC.
When you have, for example, eight sixteen-bit DACs driven from sixteen shift registers and you add or average their output signals, I would call it an eight-tap sixteen-bit FIRDAC.
Assuming uniform weighting, the first version would ideally give you nine possible output levels and the second version 524281 possible output levels, but still, the wordlengths are never greater than 1 and 16, respectively. You just get more words than in a plain DAC.
When you have, for example, eight sixteen-bit DACs driven from sixteen shift registers and you add or average their output signals, I would call it an eight-tap sixteen-bit FIRDAC.
Assuming uniform weighting, the first version would ideally give you nine possible output levels and the second version 524281 possible output levels, but still, the wordlengths are never greater than 1 and 16, respectively. You just get more words than in a plain DAC.
Aha, yes you're absolutely right.
Yet I'm not really sure if the 8-taps 1 bit dac should be considered a 1 bit dac though. There's 7 more bits at any given time at the output than the data stream originally has, so you could argue that the data is 9 times more which would make it sort of a 3 bit dac, if it would be pcm. It's just that you get a fast rate of change and low resolution exchanged for a slower rate of change (low pass filter function) with more resolution. If it would solely be a low pass filter, phase noise wouldn't lower, at least that' s how I look at it now.
I'm curious though how downsampling is done from dsd to pcm, there must be more to it than this right, or would a, let's say, 256 taps 1-bit dac be equivalent to 16 bits pcm?
Edit: 9 times, 8 times more, where are we at?
With eight equally-weighted bits, there are ideally nine possible levels. If each bit is either 0 or 1 and you add them, the possible sums are 0, 1, 2, 3, 4, 5, 6, 7 and 8 - nine values.
A nice feature of a single-bit FIRDAC is that mismatch only affects the frequency response (especially the stopband), it doesn't introduce distortion. In a multibit DAC, mismatch does introduce distortion, especially on low-level signals. The reduction in sensitivity to jitter is indeed comparable to what you have with a multibit DAC: smaller steps, so smaller impact when the step is not exactly at the correct moment.
If you want to convert DSD to PCM, you just have to digitally low-pass filter and decimate it. You need a pretty good low-pass filter to suppress ultrasonic noise and aliases, so a uniformly weighted FIR won't do the trick.
A nice feature of a single-bit FIRDAC is that mismatch only affects the frequency response (especially the stopband), it doesn't introduce distortion. In a multibit DAC, mismatch does introduce distortion, especially on low-level signals. The reduction in sensitivity to jitter is indeed comparable to what you have with a multibit DAC: smaller steps, so smaller impact when the step is not exactly at the correct moment.
If you want to convert DSD to PCM, you just have to digitally low-pass filter and decimate it. You need a pretty good low-pass filter to suppress ultrasonic noise and aliases, so a uniformly weighted FIR won't do the trick.
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Thanks for the clear answer Marcel.
It also is much easier to implement in real life, hence the many diy versions of the many-taps 1-bit FIR-dac.
Btw:
Did anyone try the AMSDM7-512 version of HQPlayer yet and hear the difference (absence) of modulation artifacts? It works at dsd256 and 512 rates and it's a real aoover for the artefacts. Dunno if other pcm to dsd converters have anything similar, but my guess is they don't.
It also is much easier to implement in real life, hence the many diy versions of the many-taps 1-bit FIR-dac.
Btw:
Did anyone try the AMSDM7-512 version of HQPlayer yet and hear the difference (absence) of modulation artifacts? It works at dsd256 and 512 rates and it's a real aoover for the artefacts. Dunno if other pcm to dsd converters have anything similar, but my guess is they don't.