guido said:
This is confusing.
Do you mean this ?:
MSB XXXXXXXXXXXXX LSB MSB data
1111111111111100 WS
1111111111111110 WS delay
0000000000000010 WS XOR WSdelay
Why data is only 15 bits ???
i suspect because all these ways for building an inverted dataword will lose one bit resolution. This is why we need a real inverted twos complement word and format it in a way we can clock it syncronous with the noninverted, both full 16bit resolution in the DAC. This is the original problem.
chatbox mode:
Dont count bits, meant to give only examples!!!
from the 8412 timing diagram we see:
MSB is one clock behind SCK. LSB is halfway the FSYNC. Ok it's a 32 bit dataword (I2S does not specify the number of bits in a frame or the framelength, so all could be more or less).
Suppose i can get something which does only output 16 bits words. Than a LSB would be before a MSB. From the diagram again, just after FSYNC toggled. So an exclusive or on FSYNC and a delayed FSYNC (with one clockpulse) would 'indicate' the LSB. See my 'timingdiagram'.
Once we have an indication on the LSB we can use it to control the inverting logic to not invert the dataline:
in lsb indicator out
0 0 1
0 1 0
1 0 0
1 1 1
(this is meant to be a table)
Yes, another xor is required to do this.
As for why the inverse of two's complement is toggle all bits but lsb, check the application note.
greetings,
Dont count bits, meant to give only examples!!!
from the 8412 timing diagram we see:
MSB is one clock behind SCK. LSB is halfway the FSYNC. Ok it's a 32 bit dataword (I2S does not specify the number of bits in a frame or the framelength, so all could be more or less).
Suppose i can get something which does only output 16 bits words. Than a LSB would be before a MSB. From the diagram again, just after FSYNC toggled. So an exclusive or on FSYNC and a delayed FSYNC (with one clockpulse) would 'indicate' the LSB. See my 'timingdiagram'.
Once we have an indication on the LSB we can use it to control the inverting logic to not invert the dataline:
in lsb indicator out
0 0 1
0 1 0
1 0 0
1 1 1
(this is meant to be a table)
Yes, another xor is required to do this.
As for why the inverse of two's complement is toggle all bits but lsb, check the application note.
greetings,
guido said:
Why not invert the LSB ???
I can not see any 32 bit word
After falling edge of FSYNC and after on clock cycle of SCK the next 16 bits are data word left.
After rising edge of FSYNC and after on clock cycle of SCK the next 16 bits are data word right.
So, can we do it like inverting and incrementing all the 16 bit words ?
Guido,
there is no such thing as "halfway the FSYNC" nor is there a 32 bit data word.
One clock cycle after leading edge of FSYNC
indicates start of right side 16 bit data word.
In this respect the timing diagram is unmistakable, or the data sheet is simply wrong.
there is no such thing as "halfway the FSYNC" nor is there a 32 bit data word.
One clock cycle after leading edge of FSYNC
indicates start of right side 16 bit data word.
In this respect the timing diagram is unmistakable, or the data sheet is simply wrong.
The CS8412 sends 32 bits while WS/Fsync is high (low) In I2S it could also be 20, 42 or 113 doesn´t matter. We need only a part of these 32 or how many you want bits, and those are 16. They are our sample and they are at pos. 2 to 17 of those 32 (or 42 or ...)
What we need for the DAC afer inverting is for the left channel DAC 16Bit noninverted+16 Bit inverted and same for the right channel DAC.
What we need for the DAC afer inverting is for the left channel DAC 16Bit noninverted+16 Bit inverted and same for the right channel DAC.
off topic ?
Why all the hassle if we want a balanced output ?
Couldn't we make an additional output stage that gives inverted output voltage ?
And balanced output makes only sense if everything is balanced (?).
I would be more interested in splitting left and right, so 2 chips for right channel and 2 for left.
Even this makes no difference.
Just looks nicer.
Why all the hassle if we want a balanced output ?
Couldn't we make an additional output stage that gives inverted output voltage ?
And balanced output makes only sense if everything is balanced (?).
I would be more interested in splitting left and right, so 2 chips for right channel and 2 for left.
Even this makes no difference.
Just looks nicer.
#59 , #62 ff
off topic:
i want something that looks like this, only outputstage D1 instead
off topic:
i want something that looks like this, only outputstage D1 instead
An externally hosted image should be here but it was not working when we last tested it.
as i understand: yes. 2 - 17 are our noninverted twos complement formatted sample, the others forgett about.
Bernhard said:
Because it is not what we want to have
I can, page 21 of the 8414 datasheet. Suggest you read it.
No 32 bits are present, 16 are meaningfull
ditto
No. We want to do inverting except LSB:
0001 inverted = 1111. thats inverting (1110) and incrementing +1
1110 inverted = 0000. thats inverting (0001) and DECREMENTING
PS found a chip: CS8415 has a mode with 16 bit i2s datawords.
Re: off topic ?
I (we?) want to cancel out noise on the DACs voltage lines. So it makes sence to use balanced dacs and unbalanced out.
Bernhard said:
I (we?) want to cancel out noise on the DACs voltage lines. So it makes sence to use balanced dacs and unbalanced out.
till said:
Nearly, the DAC would also accept 32 bit words. All the non-os mods go from 16 bit word (7220 output) to 32 bit word (7210 output). So a big CPLD fed with 32 bit words from 8414 with correct data inversion and 32 bit out would also work.
As i can only easily do the inversoin with 16 bit words, a
receiver like 8415 would do the job for me.
And 16 bit words mean half a bitclock frequency! So ~1.4 MHz.
Less noise on the PCB, but (sh*t) i also need to modify my
clock divider (two more cuts and wires..).
gr,
am i stupid?
'0001' in twos complement is 1., -1. is '1111' ok
'1110' is -2., +2. would be '0010' and not '0000'
'0000' is 0.
'1110' = -2. inverted would be inc(inc(1110))=inc(0001)='0010' =+2.
In case we feed 19bits each sample to the the DAC, 2nd is MSB of sample (noninverted / inverted dep. on DAC) 17 is LSB, and 18 and 19 are zero, we are half the way to feed TDA1541/43 and AD1865 with same format. Would look left justified 18 bit for the AD and right justified with "quirk" for TDAs.
we need to generate a own clock for this and trash all garbage bits.
guido said:
READ THE DATASHEET page 21
Why do you think some lines are DASHED
That 32 bit clock cycles change nothing about the fact that there is a 16 bit data word.
Not 32 bit.
Left word is inside 32 clock cycles and after leading edge of FSYNC again 32 clock cycles for right word.
Your way of explaining things is a little bit confusing, sorry.
It sounds like left and right channel are inside one single 32 bit data word.
sorry, i can´t explain better as i don´t really know more than posted in the thread. I only try to understand it myself. I don´t really know the right termini, onyl what i read and find here.
I still have some information missing.
Do we need a negative binary number ?
How does the TDA know its negative ?
Or do we need to convert in case of four bit words for simplicity:
0 to 15, 1 to 14, 2 to 13, 3 to 12, 4 to 11, 5 to 10, 6 to 9, 7 to 8... ???
is 0000000000000000 0 mA and 1111111111111111 -4mA ?
Do we need a negative binary number ?
How does the TDA know its negative ?
Or do we need to convert in case of four bit words for simplicity:
0 to 15, 1 to 14, 2 to 13, 3 to 12, 4 to 11, 5 to 10, 6 to 9, 7 to 8... ???
is 0000000000000000 0 mA and 1111111111111111 -4mA ?
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