All these risks don’t occur with SMSL/Topping devices 😀 These just work OK, measure OK, look OK and sound OK.
Enough good reasons that explain their success.
Enough good reasons that explain their success.
Last edited:
Good to know. Then I suggest you buy them.
https://www.audiosciencereview.com/...off-but-connected-to-power-still-works.38979/
Note, I do not recommend buying any AMR/iFi equipment, as a result of how the current incarnations treats customers.
Thor
Since when did this start? My experience with Ifi IPower, X power is post 2019 maybe even 2020. The Zen Stream (horror electronics) years later. Won’t buy anything by the brand anymore anyway and suggest others also not to do so. When an A brand produces higher priced stuff that dies or not works OK and Aliexpress sells fake stuff there are other choices. That context.
Of course it was teasing a little but the mentioned brands at least deliver affordable stuff that works OK for a reasonable to normal lifetime. With exceptions that can be expected for the price. Not sexy, I know 🙂
Of course it was teasing a little but the mentioned brands at least deliver affordable stuff that works OK for a reasonable to normal lifetime. With exceptions that can be expected for the price. Not sexy, I know 🙂
Last edited:
I was on my way out (with a little push) in 2018, I was completely gone in 2019.
The iPower X was a redesign with substitution of imported (Fairchild) SMPS Controllers with on board FET by mainland china made controller IC and separate FET. I was peripherally involved in the testing, but only in the sense of having an FFT held up in front of me to show the {PRC solution was as good as what I designed. I don't have the "X" but the original design I made.
I also would not buy any ifi product in production now and non that postdate my departure significantly, as I know who was responsible for the "engineering" (I use that term in the losses possible meaning) nor would I recommend it to anyone.
I did hear that the Zen Stream had more bug's than Klendathu.
Thor
Last edited:
@jean-paul
I'm wondering what your main listening audio system consists of? Do you have mostly brand named components or perhaps a mixture of both DIY with name brands?
I'm wondering what your main listening audio system consists of? Do you have mostly brand named components or perhaps a mixture of both DIY with name brands?
Don't care about brands, perceived reputation or topology but class D is OK. Also just one main lean & mean system (and of course some leftovers and spares). It is a mixture of cheap to mid priced Chinese audio, DIY and Elac loudspeakers with JET tweeters. Its desired goal is not to be Chinese or A branded, or to be DIY but to play music a nice and unobtrusive way and that is what it does. Good sound does not need to be expensive (well good loudspeakers maybe are the exception). Nor does it need to be the very best there is for satisfactory results as the most favorite music seems to be recorded worst 🙂 The devices do not deserve more time & attention than the material IMHO. Important parameters are user friendliness, good ergonomics, minimalist in useless features, high reliability and low power usage too. Just opinion, YMMV.
But let's do ThorstenL a favor and go back to "Simultaneous output Frontend for TDA1541 (and/or Universal Multibit DAC) using discrete logic - Collaborators wanted" as a new TDA1541 DAC will be created.
But let's do ThorstenL a favor and go back to "Simultaneous output Frontend for TDA1541 (and/or Universal Multibit DAC) using discrete logic - Collaborators wanted" as a new TDA1541 DAC will be created.
Last edited:
So, will anyone look at my diagrams of the logic I intend to use and confirm I did not make a big mistake? I can send an EXCEL file...
Thor
Crickets. And Cicada's. And the surf far off. And occasionally the annoying tittering of these annoying little lizards.
Peaceful. Love it.
Thor
Last edited:
@ThorstenL
I wish I knew and had the knowledge to help you out. Not sure why other members here couldn't contribute a little to help getting this project moving forward? I am very much looking forward to using the TDA1541a chips I have into a well designed DAC component! I do hope that something good will come out of this.
I wish I knew and had the knowledge to help you out. Not sure why other members here couldn't contribute a little to help getting this project moving forward? I am very much looking forward to using the TDA1541a chips I have into a well designed DAC component! I do hope that something good will come out of this.
One circuit that can be used?
(I posted it earlier, probably in some other topic...)
Data are placed in the midle of LE interval, stopped clock, I2S input. MSB invert option, LE is not moved from original location, Inverted datas for balanced mode option, optional word length, TS and PCM/AD formats...
Could be used as discrete dac interface too, i didnt add some additional circuit...
.
(I posted it earlier, probably in some other topic...)
Data are placed in the midle of LE interval, stopped clock, I2S input. MSB invert option, LE is not moved from original location, Inverted datas for balanced mode option, optional word length, TS and PCM/AD formats...
Could be used as discrete dac interface too, i didnt add some additional circuit...
.
Last edited:
Yes, but I stated from first post that this type of circuit idles not suited to optomise the TDA1541.
Creates an unnecessarily high bitclock. One main aim is to run at BCK at 16 X FS.
Here BCK will be 64 X FS.
We would be better off to just use WM8804/5 or CS8416 set to 16Bit IIS output with BCK = 32 X FS.
Thor
It does not "create" BCK, tis is the same range BCK from I2S bus. Just stopped...
It does not manage BCK with changing frequency.
More change will be to make 16 cycles BCK from 64 cycle original rate per Fs.
(One Fs cycle in I2S format contains 2 x 32 bit word = 64 bit/fs)
...
But is ti acheivable I think? I can try to make something with glue logic 🙂
I can double the BCK and double each DATA bit?
(Method could be a factor - maybe something opposite of return to zero?)
...
Main digital interface is probably USB / I2S. with stadard 2 x 32 bit per Fs. Most people are using them.
I have very good experience with original Amanero and I will contionue with it...
With some modifications. I am thinking of sort of "nest" PCB for Amanero...
SPDIF and other input iterfaces are welcome off-course. I have some WM8804 and 5 and certanly wil be present as option...
.
Last edited:
Ok, semantics. It still has a BCK Clock frequency four times of we want.
What I propose is to use 4 x 16 Bit FIFO's (74HC40105).
We use one FIFO as delay. The thing about a FIFO is that one full, the data flow stops even though the input clock keeps running.
With the FIFO full indication we know that 16 bit's are inside the FIFO.
This a single IC to do a lot.
The next stop, we need an elastic buffer that can absorb the 16 Bit data "burst" at BCK = 64 X FS and always output 16 Bit at BCK = 16 X FS.
It is obvious, that a single 16 bit FIFO is too short, so we cascade 2 pcs of 16 BIT FIFO chips.
Final logic, we have L/R data and using suitable logic we create an LE pulse that is 1 BCK wide and is also send into the FIFO. We also use this logic to invert MSB similar to how you do it.
That accounts for three of the four FIFO lanes, the fourth lane simply contains "high" and is used for flow control. Making sure we have 16 bit in the 32 bit FIFO, before starting the output clock.
The output clock run constant (once the FIFO is full) at 16 FS and we use it as BCK for the FIFO output and the TDA1541 BCK, we have LE, DataL and DataR from the FIFO.
We need 3pcs 16 pin FIFO IC's, some gates for inversion of MSB, a divider by 4 to make the new BCK, a delay of WCK by 1 BCK.
I drew out the timing diagram in excel and posted it here. I think it's a very neat way doing this.
Yup.
Well, the "easy" solution as said, is to just use WM8804/5 or CS8416. They can output BCK = 32 X FS IIS. Using an SRC4190 is also an option.
If we use a USB2IIS module with SPDIF out (most now have that) we can pass SPDIF and MCK through isolation Transformers and thus achieve galvanick isolation and format conversion easily.
The isolated MCK would be used to reclock the the lines from the SPDIF receiver and thus cancel any jitter it introduces.
That's the simplest solution, but it still leaves us with 32 X FS BCK, where we want 16 X FS.
Thor
OK Yes, first it is clear that: Main thing, if I am catching wel,l is that 1word in FIFO is actually 1 BIT
.
a) BCK has to be 1/4 of original.
b) these 4 input/output lines are actually carrying the same value that is one, 4 times in time extended, 1 original value bit
c) anw we can have 16 words of these 4 x Time BIT in the fifo.
d) this 4 x times "longer" BIT corresponds with 4 x times "smaller" BCK
...
It will be more clear with diagram
I can draw latter.
...
I think that it is posibile to have no "room" to send data to conversion with LE because in Datasheet for TS format noted that this could be 0 sec. So imeadetley after LSB is stored into DAC input register? And it will be full 16 bits populated in remaining FS time serial sequence.
.
a) BCK has to be 1/4 of original.
b) these 4 input/output lines are actually carrying the same value that is one, 4 times in time extended, 1 original value bit
c) anw we can have 16 words of these 4 x Time BIT in the fifo.
d) this 4 x times "longer" BIT corresponds with 4 x times "smaller" BCK
...
It will be more clear with diagram
I can draw latter.
...
I think that it is posibile to have no "room" to send data to conversion with LE because in Datasheet for TS format noted that this could be 0 sec. So imeadetley after LSB is stored into DAC input register? And it will be full 16 bits populated in remaining FS time serial sequence.
Last edited:
The FIFO IC to use is 74HC(T)40105.
Simply because anything else is unavailable. I would prefer to use 74ACT2226, but they are essentially unavailable.
The 40105 is a 16 pin IC with a 4 X 16 memory, that is, in/out is 4 bit wide and 16 Bit deep.
Yes.
No. A FIFO has asynchronous clocks on input and output.
We can use completely separate clocks for input and output.
We just need to make sure the FIFO neither overflows (or we can intentionally use this feature) or runs empty.
In our case FIFO 0 is sycronous with IIS BCK and is used to store 16 bit's of data from IIS Data. Only one of the 4 1 bit lanes is used. We do that by enabling the input clock when WCK delayed by 1 BCK goes low. After 16BCK the FIFO is full and no longer accepts Data. It holds the 16 MSB of the 32 bit IIS data frame.
Input BCK continues but the FIFO remains static. The MSB will be at the output.
Next WCK goes high. Input clock stops and output clock enables. Now we have data and FIFO data being clocked on the BCK. The FIFO output changes on the falling edge of BCK, data is latechec into the next FIFO on the rising edge.
So now we WCK, BCK (64X) DataL, DataR separated.
We now have two jobs.
Detected the MSB, Invert the data.
Bridge the 64X clock domain to 16X.
For that we use a pair of cascaded FIFO's that give us a 4 X 32 structure. We wait until the FIFO is half full before starting to clock data out.
So data enters as long there is a BCK. We need to gate BCK to stop after 16 Bit's, with input BCK at 64 X. Once we have 16 bit's worth of Data in our FIFO (and empty space for 16 bit more) we start the output clock continuous at 16 X FS.
We know across a single WCK cycle, 16 Bit will enter the FIFO, though this will happen within 1/4 WCK cycle and 16 bit's will exit. So the fill level of the FIFO will vary from 8 Bit (lowest) to 20 Bit (maximum).
In other words, the FIFO acts as elastic buffer between input data that comes in bursts at a high clock.and output being clocked out at a low continuous clock.
I drew out the clocks and data etc. for each block here:
Nor really. We do not repeat bits. This would be necessary with with shift registers. With FIFO's we asynchronous input and output.
So we clock one but in at an arbitrary frequency. Then clock one bit out at an arbitrary frequency.
The only stricture is that the number of bits in and out over the time it needs to run FIFO empty or full from 50% fill level is equal.
Look at my timing diagrams.
Thor
Yes I can even find this IC in local store...
I didnt mean "repaeat" as opperation, but the bit lenght will be determined with asinchroneus 1/4 of input BCK, so the content of output bit cell will be "automaticaly" be the same lenght as output clock?
What will be on other 3 inputs beside DATA line?