True. I do not suffer fools gladly. And I know a little bit of what is there to know, more than some, I'd wager.
Yes, BUT for example he shows CS8416 under IDENTICAL condition PDUR = 0 / PDUR = 1. That is also quite meaningful...
I think FET Audio using an HDD analyser. The measurements are not comparable to absolute jitter measurements, but relative comparisons can be made:
https://www.fetaudio.com/wp-content/uploads/2011/12/Jitter-Mea.pdf
He also measured the jitter on an XMOS interface, observe how much actual jitter the XMOS adds:
https://www.fetaudio.com/wp-content/uploads/2012/01/XMOS-jitter.pdf
Only the MCK is clean.
He also measured XMOS MCK with a Wavecrest, so we now have an absolute baseline on which base the comparisons, which makes his set of tests very useful, for chips already obsolete and discontinued, but inferences can still be drawn.
Look what the postman dropped of here at Casa al la Playa, at the Thai Riviera...
I need to see if I can improve the Power supplies and find a nice 12MHz crystal.
Thor
Well, stock at Mouser, Zero. 12 Weeks lead time. Price in singles nearly 12 Bux. I looked at this before.
It's a bit dear, no?
No, not deer, deer runs to fast.
Thor
Yes but maybe theese IC can be found in local stores as leftovers form ancient unsold stocks?
I found LS673 and LS674 in one local store. Price is something like 30EU per piece 🙁 ? 😡
74F637 about 50EU/piece...
I found LS673 and LS674 in one local store. Price is something like 30EU per piece 🙁 ? 😡
74F637 about 50EU/piece...
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My rule, LCSC and Mouser have no stock and it looks hard to get, it's hard to justify using.
No more than one obsolete and unreplacable part per design.
The 74HC40105 has good stock, is cheap and TI kinda say "this is part of a range we keep making".
The alternative, WM8805 and CS8416/DP7416 can output 16 Bit IIS (CS/DP need SW control) and the CS in PDUR = 0 has acceptable jitter performance for 16 Bit Audio.
The BCK is still twice of what I'd like, but lower than other options.
USB can be passed (isolated) as SPDIF from USB bridges on Amanero footprint. Isolate the MCK with transformer and use for reclock if using USB and the SPDIF RX jitter disappears.
Then we need no FIFO, no nothing, much more simple design. This is my backstop.
I just thought the 40105 idea was quite elegant and there may be some real interest.
Instead we discuss all other stuff.
Thor
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Well , we are still waiting to see a build born here from this famous " knowledge" , on the other thread a lot of word but no build , I guess it will be the same here
but like you I dont either like fools gladly
.
You realise you can take 74xxx595 as two of these are essentially 1pc of 673 and 74xxx165 as two of these are essentially 1pc 674.
Or you can use 16 bit wide Flip Flops (74xxx16374).
But 40105 is more elegant.
Thor
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Maybe he means inverting MSB becomes easy during data is parallel: so convert serial data to parallel, insert an inverter into the MSB line only, convert parallel back to serial. No...?
We need to count bit's anyway or work on WCK. So inverting the MCB is trivial.
We just need a single XOR gate in front of output FIFO (the ones that hold the data going to TDA1541) and control the second input to invert MSB.
If we want to do a series to parallel conversion for 64 Bit at the minimum in cases we need 4 pcs 74LVC16374 or 8 pcs 74HC164/595 or . We also need to delay WCK by one BCK so everything aligns.
We then need two 16 Bit serial registers. So the minimum are 4pcs of 74LVC165.
That's a lot of IC's and a lot of lines. And a lot of ground and supply line bounce.
We need a bit extra for flow control and MCB inversion etc., no that big.
A LOT of IC's.
Yes, it's easier to understand, very pedestrian and transparent. In other words inelegant.
Thor
You say in front of fifo output, but I think you mean after fifo output, right?
Elegance is not important, but function is. Also flexibility. If you design your logic in a modular way so that many projects can benefit it will be most successful. In the beginning you asked for interest: it seems you want to design this with and for the community, not for yourself...
So make an option for DAC chips that benefit from stopped clock. Make an option for use with TDA in simultaneous mode (and inverted MSB). Make an option for users that use 8x digital filters. Put optional 3state reclockers at the output that work together with the input selector (USB, SPDIF). Make a combined footprint for CS, AK WM, and DIR receivers. Now that would be a really useful project!
Elegance is not important, but function is. Also flexibility. If you design your logic in a modular way so that many projects can benefit it will be most successful. In the beginning you asked for interest: it seems you want to design this with and for the community, not for yourself...
So make an option for DAC chips that benefit from stopped clock. Make an option for use with TDA in simultaneous mode (and inverted MSB). Make an option for users that use 8x digital filters. Put optional 3state reclockers at the output that work together with the input selector (USB, SPDIF). Make a combined footprint for CS, AK WM, and DIR receivers. Now that would be a really useful project!
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No, in front. So the MCB goes into the FIFO inverted. That should be obvious.
We all have our prioities.
The main target is TDA1541, but some of the problems that are solved for this will the same other IC's need. So going form (say) 16 Bit with inverted MSB to (say) 18 Bit with non-inverted MSB becomes trivial.
The whole point is to avoid stopped clock, because it is not useful for TDA1541.
The rest already exists, so why would I spend to redo the same work?
No, it's a massive IC grave and this:
Absolutely honest. For that job use a CPLD/FPGA and add a reclocker that run's on MCK to kill the jitter. It is the correct tool.
And while you are at it, integrate the SPD RX function with a FIFO memory buffer and simple bitbanging DPLL control of a discrete crystal oscillator with voltage control. Make the whole thing usable for I2S inputs to dejitter those without ASRC. Integrate the Digtal Filter(s) you like.
All you need is a nice FPGA and/or an XCore 200, a few extra parts and a good tunable discrete clock oscillator - plenty of options for that on DIYA.
Now I already did such a system for a commercial product and I am not interested to do it again.
Thor
Ok,
Seeing where this went, my conclusion is simple. If we limit ourselves to 192khz we can use CS8416/DP7416/WM8804 to output 16 Bit IIS (including from USB).
Given IC supplies, CS8416/DP7416 with a simple MCU in SPI will do. Very primitive software project. We even have a way of supplying the USB MCK to the CS8416 and selecting the CS8416 Output to use either recovered or external MCK.
We get 6.144 MHz BCK for 192kHz sample rate.
That's a 81nS Pulse width and we can probably use slew rate limiters for a rise time at more than half that. So 40nS rise time for the slew rate limiter.
Add 1.8V capable logic reclockers. No attenuation will be needed to the TDA1540 with the correct supply (1.8V should be fine). So (say) 3 X SN74AUC1G79 in SOT-23. They are optimised for 1.8V supplies and rated up to 2.7V, very low additive phasenoise/jitter and inputs are 3.3V compatible.
With 12pF TDA1541 input capacitance we need a 3.3k series resistor as slew rate limiter. In terms of actual circuit simplicity this is likely the best. Or we use a larger external capacitor (which doesn't really change the current through the TDA1541 Input Capacitance) and cause more problems on our IC's.
From others experience it seems that > 20nS rise time is slow enough to push the BCK feed trough (and others) well below what can be measured. So not exactly what I was thinking of, but the most simple solution to as close as easily doable.
Thor
Seeing where this went, my conclusion is simple. If we limit ourselves to 192khz we can use CS8416/DP7416/WM8804 to output 16 Bit IIS (including from USB).
Given IC supplies, CS8416/DP7416 with a simple MCU in SPI will do. Very primitive software project. We even have a way of supplying the USB MCK to the CS8416 and selecting the CS8416 Output to use either recovered or external MCK.
We get 6.144 MHz BCK for 192kHz sample rate.
That's a 81nS Pulse width and we can probably use slew rate limiters for a rise time at more than half that. So 40nS rise time for the slew rate limiter.
Add 1.8V capable logic reclockers. No attenuation will be needed to the TDA1540 with the correct supply (1.8V should be fine). So (say) 3 X SN74AUC1G79 in SOT-23. They are optimised for 1.8V supplies and rated up to 2.7V, very low additive phasenoise/jitter and inputs are 3.3V compatible.
With 12pF TDA1541 input capacitance we need a 3.3k series resistor as slew rate limiter. In terms of actual circuit simplicity this is likely the best. Or we use a larger external capacitor (which doesn't really change the current through the TDA1541 Input Capacitance) and cause more problems on our IC's.
From others experience it seems that > 20nS rise time is slow enough to push the BCK feed trough (and others) well below what can be measured. So not exactly what I was thinking of, but the most simple solution to as close as easily doable.
Thor
Yes it is more "elegant", but I have a notion to explore this "fifo" 673/673 idea?
I think that multiplying 595 is not the same as 673 does? I will chekc data-sheets...
Maybe technicaly, but within the listening tests, for me, stopped clock TS mode is significantly better for TDA1541A. I was using it for TDA1540 as only acceptable format, but with small intervention on I2S/TS pcb, as it alreay was on table, tried with 16bit word with TDA1541A. And it was better, everything else remained the same, PS, IV stage, amplifiers, speakers etc...
I know that, but we count bits anyways, so inverting MSB is trivial.
Suit yourself.
If you connect them right, 2 x 595 + 2 x 165 will do EXACTLY the same as 673 + 674.
Thor
Did you use I2S attenuation and slew rate limiting?
Otherwise of course it would change the sound (I'll not debate better or worse, those are value judgements that are individual).
Thor