• The Vendor's Bazaar forum is for commercial offers and transactions. Only unmoderated members can post here.

    diyAudio provides this forum for the convenience of our members, but makes no warranty nor assumes any responsibility. We do not vet any members. Use of this facility is at your own risk. Customers can post any issues in those threads as long as it is done in a civil manner. All diyAudio rules about conduct apply and will be enforced.

Reference DAC Module - Discrete R-2R Sign Magnitude 24 bit 384 KHz

Jump to Latest
#5,047
Istvan Jozsef said:
Where I’d like to get confirmation or opinions are the following:

When I use external 3.3V for Amanero I only have to cut 1 trace as described at post #878. How to connect external 3.3V to Amanero board? To C27 as the post #878’ picture says or I can use GND and 3.3V output of the Amanero’s output connectors, does it matter?
Click to expand...

According to Domenico of Amanero just remove the resistor at L1 and connect external power to GND and 3.3V output of the Amanero board. I did that and it works.
 

Attachments

  • ext_power3V3.jpg
    ext_power3V3.jpg
    300.4 KB · Views: 817
#5,048
soekris said:
Of course, that's why the incoming jitter doesn't matter, assuming no bit errors, as it's reclocked and buffered so the dam1021 clock circuit define the jitter. But the clock oscillator and FPGA have low jitter, not as low as what's possible, but low enough that the dam1021 sounds pretty damn good.... Has actually been discussed early on in this thread.



If you look very close on the dac1101 and dam1121 pictures you might notice some small flip flops between the fpga and the shift registers 🙂
Click to expand...

So soren how much jitter is reduced because of the post flip flop circuit after FPGA is observed?
 
#5,049
Sounds like...

rhythmsandy said:
So soren how much jitter is reduced because of the post flip flop circuit after FPGA is observed?
Click to expand...

Soren needs some time for work, hahaha. And I am not sure he has the appropriate resources for actually measuring this. My understanding is that clocking in an FPGA is limited, likely because of the noisy environment. By re-aligning the data directly with the masterclock via flip flop right before conversion, the jitter level should end up right at the level of the clock accuracy, plus a little more for losses due to pcbs trace, etc...
 
#5,051
Digital Volume Control

The digital volume control being able to give us +10dB gain is something I am still unhappy with, I would rather have it stop at 0DB.
One example why is a review about the dac1101 I read there:
Soekris R2R DAC/Amp | Page 3 | Super Best Audio Friends
The reviewer complains about the 1101 compressing a bit and sounding slightly strained, compared to his tube dac.
And that after he adjusted volume by ear just going back little bit from full gain on the 1101.
What is a little bit? -5dB? -3dB? But than he is clipping transients on digital full scale mastered material (which is more or less all pop music from the last 15 years)
Clipping a few dB sounds not like hard distortion but more like he described the sound signature of the 1101.
On a commercial product without an exact visual representation of the digital gain (via digits) I would stop at 0dB full scale.
 
#5,056
I suppose that if one can attenuate without loss we can also amplify... as long as the signal don't clip it should be OK. But when it do its over.

I play my DAM with a filter with 6dB attenuation - sound always clean. I wonder how the new products behave wrt. this?

//
 
#5,057
TNT said:
I suppose that if one can attenuate without loss we can also amplify... as long as the signal don't clip it should be OK. But when it do its over.

I play my DAM with a filter with 6dB attenuation - sound always clean. I wonder how the new products behave wrt. this?

//
Click to expand...

Filter 6dB? Do you do that in the converter, or before? I have the DAC to 0db, reckon the MAC 6 dB down and have the best result. No real idea why that works better, but it does it?!?
 
#5,059
It should be doable (in firmware) that the FPGA reports clipping.
I think that would be a nice feature. The easiest is to report via serial interface. Some statistics (how many clips...) would also be nice. And perhaps even this could be put out at some unused pin for a LED indicate clipping.
 
You must log in or register to reply here.
Top Bottom