How did you do it?
The 12-14 seconds it takes the output DC drift to settle down is normal, it is expected.
It is due to the master JFETs reaching operating temperature, it has nothing to do with the PSU you use.
In your PSU there is a 240 Ohm resistor in series with 10uF capacitor, which has a time constant of 0.002 seconds.
Indeed, a measure to cut off, or short, the output for about 15 seconds or more upon turning on the buffer is called for.
It can be done with a relay which has time delay, or a manual switch.
... How did you do it? ...
I do not know, Joshua!
Answer 1: the DMM is lying? But my HP 3478A is showing the same value!
Answer 2: I have done a good layout? I do not believe! Do not argue on the routing of the power tracks, please!
Answer 3: Werner has given me 2 sets of very well matched FETs! I think so!
Answer 4: I have had some luck. I think so!
Best regards - Rudi_Ratlos
I do not know, Joshua!
Answer 1: the DMM is lying? But my HP 3478A is showing the same value!
Answer 2: I have done a good layout? I do not believe! Do not argue on the routing of the power tracks, please!
Answer 3: Werner has given me 2 sets of very well matched FETs! I think so!
Answer 4: I have had some luck. I think so!
Best regards - Rudi_Ratlos
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When a thread gets to 500+ posts its bound to wander. I would suggest that if any participant feels the questions are becoming repetitive or the discussion is going nowhere then perhaps its best for those involved to just withdraw and let others take up the baton of answering.
Don't make it personal. Offending posts will be removed.
I read the same think in another post somewhere on the web.
Perhaps the Siliconix devices are better in certain areas of performance?
Not everything written on the web is a factual truth, not necessarily, not always.
As long as you know the gate, D and S are just arbitrary markings and are the same electrically, it doesn't matter which way around you connect it (just JFET's)
Swapping of D & S applies particularly to RF duty jFETs.
It is rarely explicitly stated that each jFET is swappable D to S.
I have tested a few k170, swapping between D&S using my LTP style jig and I find there are differences that do show in my method.
But my method is particularly sensitive to small differences in parameters.
It is rarely explicitly stated that each jFET is swappable D to S.
I have tested a few k170, swapping between D&S using my LTP style jig and I find there are differences that do show in my method.
But my method is particularly sensitive to small differences in parameters.
What is your method and what are the differences you found?
The way JFET are constructed, there is no difference between D and S.
Another ignorant question, before to connect the buffer to the PSU LM317/337 I adjusted the PSU to give +-15VDC without load, when I connected the buffer to the PSU the voltage down to +3,91 VDC and -1,19VDC, the tx is 0-22VAC 1A main filter cap is 4.700uF