You can use Mjona's file and disconnect the buffer. The other file has been tinkered with in some way and it is too much effort to figure out why.
Kirchoff's law is one way of saying, everything affects everything else. The capacitors alter the gain of Q14 and Q15, albeit in a small way. The behavior is disguised by near on set of oscillation. Once the design is stable you can start to see more subtle effects. Have you made the modifications I suggested?
The capacitors should be on the other side of R14 and R15 for decoupling. For the sim they are not needed.
Kirchoff's law is one way of saying, everything affects everything else. The capacitors alter the gain of Q14 and Q15, albeit in a small way. The behavior is disguised by near on set of oscillation. Once the design is stable you can start to see more subtle effects. Have you made the modifications I suggested?
The capacitors should be on the other side of R14 and R15 for decoupling. For the sim they are not needed.
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Yes, I did in the schematic as you sugested, however the same result. Or did you mean in a real circuit? I agree these caps were in wrong place.
Btw, I don't understand the reason to use a buffer in such a way. If we need SE drive with balanced input we can leave other input floating, if this schematic would work.
The problem here in the input stage. The simulation of it alone showed it cannot accept full range differential input signal, it only works with 1K signal without issues. However, it could be there is some mistake in simulation which I'm not familiar enough.
Btw, I don't understand the reason to use a buffer in such a way. If we need SE drive with balanced input we can leave other input floating, if this schematic would work.
The problem here in the input stage. The simulation of it alone showed it cannot accept full range differential input signal, it only works with 1K signal without issues. However, it could be there is some mistake in simulation which I'm not familiar enough.
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When you open the parameters for the signal source you must add AC amplitude 1 and AC phase 0 on the right hand side. The AC analysis works if you do that. Add the directive .ac oct 500 10 100meg or enter it manually. However something is wrong with the Transient analysis. You need to use Mjona's version.
Disconnect the Zobel and you will see a difference in the phase plot.
Also reducing base resistors of power devices to 1R helps. Because this design is trying to squeeze too much bandwidth, the input capacitance is having an effect, even with 10R.
Verify with sim.
Disconnect the Zobel and you will see a difference in the phase plot.
Also reducing base resistors of power devices to 1R helps. Because this design is trying to squeeze too much bandwidth, the input capacitance is having an effect, even with 10R.
Verify with sim.
Actually cancel that change to the base resistors. Maybe OK. Design now seems stable with 8R in parallel with 0.005uF. No Zobel network. You can delete Zobel while trying to improve stablility.
I changed Mjona's file. Without Zobel the circuit is little unstable. There is 1K input frequency is set, I don't know how to change it.
As I understand there is +45db gain? What the second dot line means?
As I understand there is +45db gain? What the second dot line means?
Firstly, you need to take a tutorial on how to use LTspice. This is not a training thread. There are resources for this. This exercise will be hopeless until you do that.
The AC plot shows gain as a solid line and phase as a dashed line. The frequency is set with Mjona's spice directives on the left-hand side. .param Freq=20k. I don't know where you are getting 1KHz from. The transient analysis shows clipping in your file. Therefore reduce the levels of the signal generators. You have not implemented my changes in this file.
The AC plot shows gain as a solid line and phase as a dashed line. The frequency is set with Mjona's spice directives on the left-hand side. .param Freq=20k. I don't know where you are getting 1KHz from. The transient analysis shows clipping in your file. Therefore reduce the levels of the signal generators. You have not implemented my changes in this file.
Under the positive input source mentioned 1K. I tried your changes with compensation caps, but plot shows better result (without peek) with Mjona's capacitors placement. I changed them as you sugested btw.
You did not change the resistors. The 1Khz in the schematic is a comment not a directive.
As I said. Learn the tool. Don't waste people's time.
As I said. Learn the tool. Don't waste people's time.
I've changed the resistors, 210R on R6, R7. Also when I changed base resitors to 1R the line is even more flat. You said cancel that change to the base resistors.
I'll check how to use Lt tutorial tomorrow.
I'll check how to use Lt tutorial tomorrow.
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I suggest you take a time out for a week while you have familiarize yourself with the basics of LTspice.
causes of oscillation:
output stage too slow >> increase VAS comp caapacitor ( slows VAS stage)
to many gain stages >> causes phase shift at higher frequencies ( even very fast mosfet outputs )
triple darlington outputs = slow or phase shift
voltage feedback is slower and has an extra stage of gain. Current feedback is on the Emitter, voltage feedback on the base 100x less current.
output stage too slow >> increase VAS comp caapacitor ( slows VAS stage)
to many gain stages >> causes phase shift at higher frequencies ( even very fast mosfet outputs )
triple darlington outputs = slow or phase shift
voltage feedback is slower and has an extra stage of gain. Current feedback is on the Emitter, voltage feedback on the base 100x less current.
You can check that VAS compensation capacitor is already increased. How to speed up output stage?
Thanks.
Thanks.
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I'd try cascode, but I am as guilty as you as I don't know my LTspice 🙁
I am playing with cascoded-CFP output on a voltage FB amp and it seems promising.
Good luck and patience,
M.
The eternal beginner...
recess
Mjona can't answer anything until he returns, maybe next week (Post #428 Reasons Of Oscillations In Audio Amplifiers And Best Ways Of Elimination )
Please hold off posting further circuit changes until mjona returns.
AndriyOL, for the basics of LTspice I recommend start on these for forums:
Settings used for .trans how to measure V, I, P values using cursors, and .ac runs,
How to read gain and phase using the cursors
How to screen capture circuits and plots and upload to diyAudio posts
How to set up .four parameters and read the ErrorLog tables, generate plots and use cursors to read relative levels of each harmonic and capture plots for uploading
Stepping parameters and component values with curly brackets
Basic schematic entry and editing.
BTW Bob Cordell's 1st Ed has a good chapter on getting started in LTspice (probably still in 2nd Ed). There may be similar tutorials on diyAudio but I haven't searched it out. Anyone recommend a link?
To all: This thread has been the most ambitious one I have seen on diyAudio to help a beginner because:
1) it started with a circuit with a muffed input stage [#439 Reasons Of Oscillations In Audio Amplifiers And Best Ways Of Elimination ], and
2) it used a CFP triple output stage that is known to cause oscillation problems [#280 Reasons Of Oscillations In Audio Amplifiers And Best Ways Of Elimination ] and most experienced designers avoid it, and
3) it uses a speed up capacitor across the T resistor between bases of the power transistors which can cause cross-conduction latching [#313 Reasons Of Oscillations In Audio Amplifiers And Best Ways Of Elimination], and
4) the thread starter did not know how to use LT and had limited knowledge of amplifier design basics.
Mjona has done a super class-A job to help AndriyOL.
BTW With a Rush input stage like I suggested [#422 Reasons Of Oscillations In Audio Amplifiers And Best Ways Of Elimination ] my simulations suggest close to 1ppm distortion at 20kHz and 20W.
So AndriyOL please keep on with this design (mjona too). The main problems have already been overcome to make it work. I think it could become one of the top diiyAudio Solid-State amps so far.
Cheers
Mjona can't answer anything until he returns, maybe next week (Post #428 Reasons Of Oscillations In Audio Amplifiers And Best Ways Of Elimination )
Please hold off posting further circuit changes until mjona returns.
AndriyOL, for the basics of LTspice I recommend start on these for forums:
Settings used for .trans how to measure V, I, P values using cursors, and .ac runs,
How to read gain and phase using the cursors
How to screen capture circuits and plots and upload to diyAudio posts
How to set up .four parameters and read the ErrorLog tables, generate plots and use cursors to read relative levels of each harmonic and capture plots for uploading
Stepping parameters and component values with curly brackets
Basic schematic entry and editing.
BTW Bob Cordell's 1st Ed has a good chapter on getting started in LTspice (probably still in 2nd Ed). There may be similar tutorials on diyAudio but I haven't searched it out. Anyone recommend a link?
To all: This thread has been the most ambitious one I have seen on diyAudio to help a beginner because:
1) it started with a circuit with a muffed input stage [#439 Reasons Of Oscillations In Audio Amplifiers And Best Ways Of Elimination ], and
2) it used a CFP triple output stage that is known to cause oscillation problems [#280 Reasons Of Oscillations In Audio Amplifiers And Best Ways Of Elimination ] and most experienced designers avoid it, and
3) it uses a speed up capacitor across the T resistor between bases of the power transistors which can cause cross-conduction latching [#313 Reasons Of Oscillations In Audio Amplifiers And Best Ways Of Elimination], and
4) the thread starter did not know how to use LT and had limited knowledge of amplifier design basics.
Mjona has done a super class-A job to help AndriyOL.
BTW With a Rush input stage like I suggested [#422 Reasons Of Oscillations In Audio Amplifiers And Best Ways Of Elimination ] my simulations suggest close to 1ppm distortion at 20kHz and 20W.
So AndriyOL please keep on with this design (mjona too). The main problems have already been overcome to make it work. I think it could become one of the top diiyAudio Solid-State amps so far.
Cheers
I did not check this circuit on square wave input at 10kHz - the buffer amplifier is ac at both ends the main input is dc coupled - a combination which results in a significant series of dc voltage pulses at the output.
To obviate that issue the main amplifier input needs to be ac coupled by including a series input capacitor of 100 uF.
To obviate that issue the main amplifier input needs to be ac coupled by including a series input capacitor of 100 uF.
My file was stable before you altered it. I said if you wanted to alter the voltage rails as you have now done the circuit would remain stable.
What happens when voltage rails are reduced the Miller capacitance around any common emitter stage - that is one with a resistor/CCS load in series with the collector - will increase.
So whatever Vas compensation capacitor values there are these will need to be altered.
The reason for this is that Miller capacitance in a planar transistor is directly proportion to the area of the collector to base junction and inversely proportionate to the square root of the voltage seen at the collector.
C2 and C33 in the .asc attached refer - are now 22 p. The stability margin in the Bode test is 45 degrees. These caps are shown connected as they should be so don't alter them again.
You have been pretty determined to have your way on getting a balanced input against a lot of advice - including mine.
I have shown in the attachment how this can be connected up and tested with a 10kHz square wave input signal using capacitor coupling at both input ends.
The capacitor at the output of 2uF is a good stability test and the square wave shape ahead of the output coil - test probe at V(n032) looks fine. The disruption you see after the coil is a long way outside the audio range.
I have not run a Bode plot test on the circuit in this balanced configuration nor adjusted the dc offset or output Iq. You will have picked up from recent experience how to deal with these things.
One contributor has suggested there is some learning one has to take up for oneself - in particular with LTSpice. There is a tutorial thread you could check out on this site or seek advice on that subject.
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