Just reading a Jim Williams AN for a second time and things are dropping. First the PSRR for the 3042 will be good for low to medium noise but from the AN Jim seemed to use ferrite pi filters targeting the high frequency that the 3042 cannot. He added ferrite beads in this fashion post 3042 to n the load and before the 3042.
My thinking here is the noise for the mains etc will find some large input 15mF caps useful. However the low-mid frequency then cover PSRR but following that the high frequency (ie 24.576MHz and harmonics) then falls to the ferrite bead pi filter.
My thinking here is the noise for the mains etc will find some large input 15mF caps useful. However the low-mid frequency then cover PSRR but following that the high frequency (ie 24.576MHz and harmonics) then falls to the ferrite bead pi filter.
AN101 (https://www.analog.com/media/en/technical-documentation/application-notes/an101f.pdf) although not the 3042 specifically.
I spent yesterday (after the CDP cap BOM finalisation) on kicad working on the design for the LT3080DD regulators and some adjustments on the clock board schematic.
The clock board, for some strange reason I put a cap in the clock path design however this has changed to an optional resistor for any impedance adjustment. I will probably create a new PCB starting at the clock traces then bringing in the 3042 design to modify from the existing PCB.
As I have a large sheet of photo resist for etching, I want to have multiples of the board on the PCB layout and then use the remainder of the board area for multiple low voltage and high voltage power supplies if there's space.
My thinking for the PCB etches will be to print the circuits using a laser printer onto some laser-compatible transparent sheets but have the image in reverse with the toner side facing the copper (which corrects the reverse). That means there's less space for light to be spread compared to putting the toner on the top (the transparent layer will scatter the light thus blurring the image).
The LT3080DD are micro small and with the copper PCB with some fine solder based vias to copper on the underside to distribute heat. I reckon that the 1oz copper PCB may get up to 2W of dissipation so the input to output voltage difference will need to be quite small (ie around 1-2V max). If I switched top aluminium clad PCBs that could get to 5W. So for the 15V supply, the input may be 16V max with these packages - I'll add a couple of voltage protection diodes on the front end for this (may be over engineering) and I also want to add some pad spaces for ferrite beads and caps for optional pi filters on the power lines.
The other point is that as the tracks are so fine for both the clock board and the LT3080DD packages (although they do have multiple pins for the main input and output - just the SET pin remains but it's on a corner so I may not have a thin track issue) that all odd techniques are needed to prevent the light scattering or the copper etch timing from destroying the tracks.
My thinking here is to make a couple of circuits of slightly different PCB layouts (with etching in mind, with interference protection ideas and to protect from etching process mistakes) to minimise the dead space on the etch.
For a different project - I have a double sided and a single sided photo resist board. For the HV regulator I may simply move my prototype from the matrix board to the single sided board etch with some improvements as these will be running at 180+V. I also want to make a voltage doubler board so we're looking at ~240Vdc on the large heatsinked 5 pin LT3080 that I have from before (these work well at HV with a mosfet running as a maida-style). The prototype matrix board was happy at 160-180Vdc for extended periods.
I have the components for the 5V to 3.3V regulators for the clock, I have some but not all of the 5V and 15V (I have the 3080 but need to get the SMT resistors for example to match modelling). I also need a couple more trim pots for the new boards and some wiring.
So no photos but there's been some progress!
The clock board, for some strange reason I put a cap in the clock path design however this has changed to an optional resistor for any impedance adjustment. I will probably create a new PCB starting at the clock traces then bringing in the 3042 design to modify from the existing PCB.
As I have a large sheet of photo resist for etching, I want to have multiples of the board on the PCB layout and then use the remainder of the board area for multiple low voltage and high voltage power supplies if there's space.
My thinking for the PCB etches will be to print the circuits using a laser printer onto some laser-compatible transparent sheets but have the image in reverse with the toner side facing the copper (which corrects the reverse). That means there's less space for light to be spread compared to putting the toner on the top (the transparent layer will scatter the light thus blurring the image).
The LT3080DD are micro small and with the copper PCB with some fine solder based vias to copper on the underside to distribute heat. I reckon that the 1oz copper PCB may get up to 2W of dissipation so the input to output voltage difference will need to be quite small (ie around 1-2V max). If I switched top aluminium clad PCBs that could get to 5W. So for the 15V supply, the input may be 16V max with these packages - I'll add a couple of voltage protection diodes on the front end for this (may be over engineering) and I also want to add some pad spaces for ferrite beads and caps for optional pi filters on the power lines.
The other point is that as the tracks are so fine for both the clock board and the LT3080DD packages (although they do have multiple pins for the main input and output - just the SET pin remains but it's on a corner so I may not have a thin track issue) that all odd techniques are needed to prevent the light scattering or the copper etch timing from destroying the tracks.
My thinking here is to make a couple of circuits of slightly different PCB layouts (with etching in mind, with interference protection ideas and to protect from etching process mistakes) to minimise the dead space on the etch.
For a different project - I have a double sided and a single sided photo resist board. For the HV regulator I may simply move my prototype from the matrix board to the single sided board etch with some improvements as these will be running at 180+V. I also want to make a voltage doubler board so we're looking at ~240Vdc on the large heatsinked 5 pin LT3080 that I have from before (these work well at HV with a mosfet running as a maida-style). The prototype matrix board was happy at 160-180Vdc for extended periods.
I have the components for the 5V to 3.3V regulators for the clock, I have some but not all of the 5V and 15V (I have the 3080 but need to get the SMT resistors for example to match modelling). I also need a couple more trim pots for the new boards and some wiring.
So no photos but there's been some progress!
So, as always a slow plodder, I've been reading up more on clocks and high speed PCB design. If anyone is interested here are a couple of URLs that I found interested (I know a bit but not enough, these have answered some of the questions).
The first thing to understand is that this is a square wave hence this is not just a ~25MHz but should take into account the harmonics required to recreate the square wave, hence we're looking at 250MHz or 500MHz bandwidth .. so taking into account higher speed ideas is important. So as long as the traces are short (ie IIRC 7.5cm or below to stop the harmonics causing issues) we should be good.
1. pcb-design-hints-rf-pcb
2. pcb-layout
3. https://www.emcstandards.co.uk./files/part_5_text_and_graphics_21_may_09.pdf
So I have a design that has I/O in terms of three ports with a ground that connects each to the ground of the target board. This may or may not be the best idea (think ground loops and erroneous flows noise currents through ground). So I will built in the option to link or cut the link between the ground planes for these SMB connectors. In theory this should provide the return path so for now they will be kept in.
As I have a 2 layer FR4 board, it may not be as noise less as a 4 layer board but I can use micro strip co-planar so there is a ground behind the signal track and an attached ground either side where possible. I may be restricted using the 2 layer but it's possible.
Next to match the impedances to reduce/remove reflections I will make space for matching resistors between the signal track and ground. The last thing I want is a large reflected signal from a high impedance reflecting back at a higher amplitude and taking out my new oscillator :/
I've settled on 50ohms as that's what the ADC uses and so I'll use that across the board too.
So the design has an oscillator that will drive a clock buffer. This protects the signal integrity, the track will have a solid copper ground plane behind with ground either side with vias. This should reduce the emitted clock noise from the track. The buffer has three outputs - one to each SMB and those will use the same coplanar micro strip to prevent the clock signal radiating.
The other point is that the SMB connectors will be all on one side of the board and the power with it's ground link will also be on that side to prevent flows of current across the board.
The clock will have a local power decoupling filter - a 0.1uF, a 1uF, (space for a 10uF), a 25MHz ferrite bead (actually it's a CM ferrite in Z configuration) and a 10uF then the LT3042.
I have a LT3042 for the clock buffer, it's ground will be close to the buffer. That buffer will take 50mA.
Now I have the option of using a second regulator to separate the oscillator (although the regulator will do little for the HF noise) or simply drive both from the same LT3042 then use separate pi filters to remove the HF noise with a second pi filter before the regulator.
This will keep a reasonable load on the regulator (the oscillator is 25mA so around 75-90mA below the 200mA max) but provide some removal of noise.
If I use a second regulator then it will only be fighting the lower frequency input ripple and the low load may cause additional issues. So as long as the filters aren't fighting each other or (as inductors do by in parallel, reduce the inductance), then I may simply design for a single regulator.
The first thing to understand is that this is a square wave hence this is not just a ~25MHz but should take into account the harmonics required to recreate the square wave, hence we're looking at 250MHz or 500MHz bandwidth .. so taking into account higher speed ideas is important. So as long as the traces are short (ie IIRC 7.5cm or below to stop the harmonics causing issues) we should be good.
1. pcb-design-hints-rf-pcb
2. pcb-layout
3. https://www.emcstandards.co.uk./files/part_5_text_and_graphics_21_may_09.pdf
So I have a design that has I/O in terms of three ports with a ground that connects each to the ground of the target board. This may or may not be the best idea (think ground loops and erroneous flows noise currents through ground). So I will built in the option to link or cut the link between the ground planes for these SMB connectors. In theory this should provide the return path so for now they will be kept in.
As I have a 2 layer FR4 board, it may not be as noise less as a 4 layer board but I can use micro strip co-planar so there is a ground behind the signal track and an attached ground either side where possible. I may be restricted using the 2 layer but it's possible.
Next to match the impedances to reduce/remove reflections I will make space for matching resistors between the signal track and ground. The last thing I want is a large reflected signal from a high impedance reflecting back at a higher amplitude and taking out my new oscillator :/
I've settled on 50ohms as that's what the ADC uses and so I'll use that across the board too.
So the design has an oscillator that will drive a clock buffer. This protects the signal integrity, the track will have a solid copper ground plane behind with ground either side with vias. This should reduce the emitted clock noise from the track. The buffer has three outputs - one to each SMB and those will use the same coplanar micro strip to prevent the clock signal radiating.
The other point is that the SMB connectors will be all on one side of the board and the power with it's ground link will also be on that side to prevent flows of current across the board.
The clock will have a local power decoupling filter - a 0.1uF, a 1uF, (space for a 10uF), a 25MHz ferrite bead (actually it's a CM ferrite in Z configuration) and a 10uF then the LT3042.
I have a LT3042 for the clock buffer, it's ground will be close to the buffer. That buffer will take 50mA.
Now I have the option of using a second regulator to separate the oscillator (although the regulator will do little for the HF noise) or simply drive both from the same LT3042 then use separate pi filters to remove the HF noise with a second pi filter before the regulator.
This will keep a reasonable load on the regulator (the oscillator is 25mA so around 75-90mA below the 200mA max) but provide some removal of noise.
If I use a second regulator then it will only be fighting the lower frequency input ripple and the low load may cause additional issues. So as long as the filters aren't fighting each other or (as inductors do by in parallel, reduce the inductance), then I may simply design for a single regulator.
Mark2 board. Not finished by a mile but I'm feeling happier with the basic layout where I'm trying to minimise the return current loops.
The idea is to use a big centre ground in the middle. The voltage will come from pads on with the 560uF so that the ground between the ground and the SMB grounds are close so it doesn't end up flowing across the board.
I still need to model/test the ferrite bead arrays I'm intending to use but the data sheet shows a decent impedance at about 24MHz.
A solid back ground plane will be put in, vias to transfer heat from the regulator as well as along the signal path to to make them coplanar.
That's the sort of thing I'm thinking of, just need todo pen+paper calculations first as the new ferrites will drop the DC voltage a tad. I may end up changing the regulator caps for some film caps (larger) but we'll have to see. Also a THT trim pot may be an idea.
The idea is to use a big centre ground in the middle. The voltage will come from pads on with the 560uF so that the ground between the ground and the SMB grounds are close so it doesn't end up flowing across the board.
I still need to model/test the ferrite bead arrays I'm intending to use but the data sheet shows a decent impedance at about 24MHz.
A solid back ground plane will be put in, vias to transfer heat from the regulator as well as along the signal path to to make them coplanar.
That's the sort of thing I'm thinking of, just need todo pen+paper calculations first as the new ferrites will drop the DC voltage a tad. I may end up changing the regulator caps for some film caps (larger) but we'll have to see. Also a THT trim pot may be an idea.
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Thinking about it, it makes sense to put the ferrites in series, just like the tube power supplies. Not only does it prevent halving of the inductance but the high current closer to the regulator, the more sensitive signal generation at the end of the chain so it gets two sets of filtering. I may need to adjust the regulator resistor values to set the output voltage as the ferrites will drop some but I hope not too much.
I could use the ferrites (actually small ferrite common mode chokes) on the return of the oscillator if I bring matched length traces back it could work to reduce noise however 2 layer makes this difficult.
The concern I have is the return path for the ground of the oscillator goes around the circuit board, the outward leg on the right and the return (plus any decoupled noise) then returns around the left. That's a big loop. Perhaps it's better for the oscillator to have it's own path back past the regulator thus not going past the output signals. I could move the regulator and power supply filtering down and then rotate the oscillator to make the ground return easier. The larger the loop the bigger the antenna.
Although there will also be a ground plane underneath so I suspect the majority of the ground will go via the back plane. I will probably then have a three prong front ground plane acting like a star ground - one side for the output and shielding, one for the middle noise reduction/filtering and the other new one on the right taking the oscillator and power supply return. I would probably remove the link between the regulator circuits and ground and the new ground.
The issue is I can't make a split plane on the back as I have some power lines crossing where the gaps would be which is worse than having a single rear ground plane.
Perhaps I'm fussing over the return, given the current will find the lowest impedance (ie the large rear ground plane) and any return current will flow that path anyway.
For the vias I'm going to use a jewellers fine drill (I have a Dremel on a drill press) to make thin wire holes and then use some wire and solder to make a rudimentary via.
I could use the ferrites (actually small ferrite common mode chokes) on the return of the oscillator if I bring matched length traces back it could work to reduce noise however 2 layer makes this difficult.
The concern I have is the return path for the ground of the oscillator goes around the circuit board, the outward leg on the right and the return (plus any decoupled noise) then returns around the left. That's a big loop. Perhaps it's better for the oscillator to have it's own path back past the regulator thus not going past the output signals. I could move the regulator and power supply filtering down and then rotate the oscillator to make the ground return easier. The larger the loop the bigger the antenna.
Although there will also be a ground plane underneath so I suspect the majority of the ground will go via the back plane. I will probably then have a three prong front ground plane acting like a star ground - one side for the output and shielding, one for the middle noise reduction/filtering and the other new one on the right taking the oscillator and power supply return. I would probably remove the link between the regulator circuits and ground and the new ground.
The issue is I can't make a split plane on the back as I have some power lines crossing where the gaps would be which is worse than having a single rear ground plane.
Perhaps I'm fussing over the return, given the current will find the lowest impedance (ie the large rear ground plane) and any return current will flow that path anyway.
For the vias I'm going to use a jewellers fine drill (I have a Dremel on a drill press) to make thin wire holes and then use some wire and solder to make a rudimentary via.
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Making your own PCB at least once, focus the mind on the design of it. I will probably go down that route moving forward as I can see the process being mucky and a learning curve.
I have read that a shunt regulator would work better given less impedance, the 3042 is a series. I'll look at the design - I assume this operates at a higher frequency bandwidth?
Interesting there's a sub-text on that link with LDOs etc and audible changes. This is digital so the closer to the perfect clock the better it should be.. unless you prefer some distortion 😉 (although it could be anything without further testing).
At typical DS clock frequencies (22M/24M) LT3042 has already lost most of its oomph so caps and ferrites fill in. The discrete regulator should work well and is cheaper. And much easier for PCB etching 😉
Yup i was aware of the LF vs HF pref difference. I may make another version at a later date. I have the 3042 at the moment. Let me fail with etching and soldering that first 🙂 (I will make a discrete pcb if it fits on the blank).
Here is a link to a stripline calculator to help you match the 50 Ohm cables: https://www.microwaves101.com/calculators/1202-stripline-calculator If you try to keep the clock transitions fast you will have lots of EMI to deal with. Slowing the transitions won't necessarily degrade the timing accuracy.
As long as the logic transition occurs at precisely the correct time each period without noise - I see what you mean. I assume there's a maximum limit on that due to the load imposed on the signal source (ie the oscillator or clock buffer). Almost as if a sine wave would be the best!
So I'll be using an MGChemicals #660, figures based on the datasheet:
er = 4.2 (roughly between the 1MHz and 1GHz ranges)
Tanq = 0.016 (between the two ranges of 1Mhz and 1GHz)
Rho = 1 copper
Height = 1.6mm substrate thickness
Thickness = 1.37 mils (copper thickness)
Frequency = 500MHz
The trace between the oscillator and the buffer: 0.393 mils which given the existing 9.8mil width gives a nice 75ohm figure.. Instead I need to use a 27 mil thick trace for a 50.27 ohm track with 0.01 deg angle and 0.000 dB loss. However that's too wide. We're looking at 15-20mils for the pad tracks so the only options are longer tracks or add a resistor.
Interesting source for impedance matching: https://www.ctscorp.com/wp-content/uploads/2015/10/AN1025.pdf
So this being a 3.3V TTL it seems that a series termination at the clock source also has the bonus of slowing the transition (and thus reducing the transition speed and thus EMI). I will get a double hit of this (one from the clock to buffer and one from buffer to ADC).
Playing a bit with kicad on the clearances and pours (this is still work in progress)
One thing I want to check is if the laser printer will actually print a 6 mil spacing between track and ground plane.
The way I will test the PCB (without installing the oscillator) is to use the sig gen set to 50R output and then measure the input and reflected peaks for a 24MHz signal. I can fit a SMB-BNC with 50R termination on the scope.
Not much done tonight but a step forward and an early night I think.
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The question I have at the moment is:
The ADC has a 49.9R terminating resistor (optional pads to ground but I installed one). I assume to minimise the reflections would it be better to a series resistor at the source (more symmetrical transitions). The connection between the ADC and clock buffer will be a 15cm RG316 with SMB connectors.
I think I will design in pads for series resistors, I can then tune the resistances. I may also put space for small caps to be able to take higher harmonics off to shape the corners of the transitions if needed. I'm assuming the SMB and connectors will maintain a rough stable impedance (they should).
The ADC has a 49.9R terminating resistor (optional pads to ground but I installed one). I assume to minimise the reflections would it be better to a series resistor at the source (more symmetrical transitions). The connection between the ADC and clock buffer will be a 15cm RG316 with SMB connectors.
I think I will design in pads for series resistors, I can then tune the resistances. I may also put space for small caps to be able to take higher harmonics off to shape the corners of the transitions if needed. I'm assuming the SMB and connectors will maintain a rough stable impedance (they should).
Well the laser printer almost worked with the 6 mil spacing. I've also setup a 0.5mm drill via which also looks too large, although the smallest I can get is an HSS 0.30mm which should work in the Dremel but slow drilling to prevent it from snapping. The vias under 3045 are for heat rather than simple grounding.
So it looks like possibly a 8 mil or 10 mil may be the limit of the printer (my toner is low but I have a new cartridge).
So it looks like possibly a 8 mil or 10 mil may be the limit of the printer (my toner is low but I have a new cartridge).
I've also mapped out the most "likely" low impedance routes across the solid backplane for the signal (and power) return currents. My concern is the circled area given the pink return. If I rotate the oscillator 90 degrees clockwise and move the components down that reduces the current return loop size due to the hole required under the oscillator (assume that is required in the same way that crystals require a low capacitance).
If I move the components of the power and ferrite first providing the filtering for the orange path, then it would reduce the current loop.
There's not much I can do with the red current loop - that's either coming back with the BNC shield or possibly the ground power cable depending on the impedance. That will then have to come through to the ground pin on the clock buffer.
What I'm trying todo is minimise the currents flowing across the signal paths and keep the power supply and return as close together as possible.
If I move the components of the power and ferrite first providing the filtering for the orange path, then it would reduce the current loop.
There's not much I can do with the red current loop - that's either coming back with the BNC shield or possibly the ground power cable depending on the impedance. That will then have to come through to the ground pin on the clock buffer.
What I'm trying todo is minimise the currents flowing across the signal paths and keep the power supply and return as close together as possible.
The HP laser printer seems to not like having some shapes close to the edges (centre of the SMB for example) and the registration seems not to follow the design - for example the signal path is closer to the pour on one side and not the other but in the design they're the same distance.
Will move the vias for the crystal ground pin too, too close for soldering etc. Also I need to move them away from the edges more for registration issues.
Will move the vias for the crystal ground pin too, too close for soldering etc. Also I need to move them away from the edges more for registration issues.
Ok, I think we're almost there for V1 of the PCB (some vias have been repositioned already). I also made the footprint of the cap the right size.
Next up will be to make the other regulator boards which should be relatively straight forward compared to this!
I have the 3080s which will be a test, although probably in the long run the concept of a shunt may make it better for the ADC. Not decided until I start measuring the overall performance. What I should do is look at the SMPS bench supplies output for HF and the mains for HF output to see if there's any specific noisy bands then use a ferrite and caps to help reduce that noise if that's going to cause issues at a later date (design but not populate).
There's a guy doing 4 layer boards with one layer being a one time use heating element to self solder 🤣 however I suspect a winding loop of copper (instead of a pure ground plane) is likely to make a nice inductor or mess with any higher frequency signals!
Next up will be to make the other regulator boards which should be relatively straight forward compared to this!
I have the 3080s which will be a test, although probably in the long run the concept of a shunt may make it better for the ADC. Not decided until I start measuring the overall performance. What I should do is look at the SMPS bench supplies output for HF and the mains for HF output to see if there's any specific noisy bands then use a ferrite and caps to help reduce that noise if that's going to cause issues at a later date (design but not populate).
There's a guy doing 4 layer boards with one layer being a one time use heating element to self solder 🤣 however I suspect a winding loop of copper (instead of a pure ground plane) is likely to make a nice inductor or mess with any higher frequency signals!
When looking at the ground return, even with a groung plane (current best practice) the return current will be directly below the signal and if the ground is interrupted the system is degraded. And it will radiate. You can not source and load terminate TTL type signals because you loose 1/2 of the signal. The usual practice is source termination. Most logic doesn't have the power to drive a low Z termination anyway. In the early days 220 Ohms to ground and 330 Ohms to the logic supply was practiced but I have not seen that in a generation. For high speed today LVDS (low voltage differential signalling) is used. HDMI uses a version of this for gigabit data rates.
For clock distribution I used a transformer plus a separate isolated floating supply for the oscillator and driver. This prevents data related ground modulation from affecting the clock. There are several pulse transformers that work pretty well with enough isolation. They are also used for cable TV.
For clock distribution I used a transformer plus a separate isolated floating supply for the oscillator and driver. This prevents data related ground modulation from affecting the clock. There are several pulse transformers that work pretty well with enough isolation. They are also used for cable TV.