Your interpretation seems in a reversed way.
It's better for us to interpret the protocol as "WS indicates the start of the frame in one bit clock ahead so that the receiving side may get ready before the first bit arrives."
For 32bit, the first BCLK can be the last bit from the previous LRCLK cycle..
That probably didn't make any sense... this diagram shows what I mean:
An externally hosted image should be here but it was not working when we last tested it.
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When preparing a white paper regarding the LSB extension error I discovered that there also was a two´s complement code error that needed correction for the LSB extension error correction routine to work 100% properly.
Instead of revealing the new corrected routine I decided to inform those I had given the information about the initial LSB extension error correction routine.
After a lot of analyzing, calculation and simulation I discovered that I could design a DAC that avoids both the LSB extension error and the two´s complement code error etc., and can thus receive 1 bit to 32 bit data (DSD to 32 bit PCM) regardless if the data are zero padded or true data, and convert to the correct and intended analog output values..
However if connected to a standard "dumb" I2S source it will perform as any other DAC for the 8 sample time period it uses to analyze the incoming data and apply the correct correction method.
I talked with a marketing manager of NDK (NIHON DEMPA KOGYO CO., LTD.) . He said, "The type NZ2520SD of which use for consumer audio applications is rapidly increasing is manufactured at our local Furukawa Plant. The product is 'Made in Japan'."
They have actually one plant in China not in "Shenzhen" but in "Suzhou". He said, "The plant manufactures the other kind of products".
Their NZ2520SD type offers, 11.2896, 12.288, 22.5792, 24.576, 45.1584, 49.152 MHz. A personal user can purchase it at the minimum quantity 1 at Chip1Stop webshop. Regular domestic price for 1 piece is 1,500 JPY (approximately 15 USD) and for 50 pieces 800 JPY (approximately 8 USD).
The type 7311S-DF-255R offers, 90.3168 and 98.304 MHz. A personal user can purchase it at the minimum quantity 1 at Chip1Stop webshop. However, as it is LVPECL output, you need a driver chip that converts LVPECL to CMOS level.
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The diagram is very clear, very thanks🙂
It's great to hear about it, I also always purchase from chip1stop apart from digikey, mouser and RS. They can ship from Japan to here in just one day! The hardest part of chip1stop is it's poor search engine, hard to find parts if by spec, hope it will improve soon. A design with 90.3168 and 98.304 MHz is on progress, I will try if it can use LVPECL.
NDK(non-pll) should have better phase noise than fox xpresso(ASICs/PLL), if they can also include the phase noise graph in the datasheet, it's a plus!
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Hi.
Regarding phase noise measure plot in the datasheet. It is my experience that if a osc do not have optimiced on p/n then the compagny will not show these in the datasheet.
Crystek have very low p/n osc on the needed 98/99Mhz and these have mouser or digikey.
Ps: i will be very interested in buying one xmos usb with these osc and also if the firmware support dsd(dff,dsf)
Br
Caad
I tried to find Crystek 90.3168 and 98.304 MHz pair oscillators at Digi-Key and Mouser, and just found the type 601107 98.304 MHz (+-50 ppm).
I think many people require CCHD-950 90.3168 and 98.304 MHz +-25ppm.
Would you please tell us the page, or how to select those products at Mouser or Digi-Key?
Two problems, cost and delivery on the NDK oscillators.
I requested their quote before;
Cost 7,500 JPY/each (75 USD) and about 3 months lead time for delivery.
I'm not sure whether the result is still valid or not.
As for phase noise plots, I got them from their marketing section.
Please contact to me,
bunpei < at > ta2 < dot > so-net < dot > ne < dot > jp
Hi Bunpei and Others..
I'm very sorry. I was misleading you. It was the Crystek Low P/N OSC CCHD-957 @ 45Mhz and 49Mhz...Not the 90Mhz and 98Mhz..
The CCHD-957 @ 45Mhz and 49Mhz can be found at Mouser.
These CCHD-957 har supreme P/Nspec. Please take a look at 10Hz offset.
=<100dBC. Amazing spec of a OSC without oven !!! I dont really care about if it has 50PPM or 25PPM divination as long the P/N is below 90dB @ 10Hz. These OSC are not used in an industrial envioment spec from -25C to 85C. These OSC will be placed in a Hi fi equilment and used around 20-30C. Please be aware of OSC with build in Digital PLL. These can have several ripples from 100Hz and out to 10kHz. If the manufactor specs the jitter on this type of OSC, then be aware that the Jitter properly is calculated from frequencies above 1kHz to e.g. 100Khz. The importance of a good OSC is how it handles the P/N close to the Carrier @ eg 10Hz and out to 10Khz. (I believe all folks in this forum can hear frequencies in this frequency range. )
Br
Caad
Please see attachment of P/N measurement. Ref is a Oven OSC @ 10MHz. Do not take attention to the Spikes. these came from other noisy equipment during this measurement. Jitter calculated for this Oven OSC: 135fs @ 10-10kHz.
The upper curve is the OSC with build in DPLL. Check the abnormal ripple from 10Hz to 10kHz. This OSC is a Si530 (24.576) with calculates jitter 2.3ps @10Hz - 10kHz(SPec on datasheet is: 0.6ps @ 12Khz ->20MHz), but others with DPLL may measure the same ripple?. The middle curve is a TCXO (24.576).
Attachments
Eventually NDK released an easy-reading document that illustrated an importance of low phase noise oscillators in consumer audio applications, today on their website. The document is written in Japanese only. However, you can look at a figuare of phase noise plots of their typical products.
The title in Kanji characters means "Phase Noise Comparison of Crystal Oscillators".
The OCXO type referenced in the graph above is used in a TAD CD player.
The title in Kanji characters means "Phase Noise Comparison of Crystal Oscillators".
The OCXO type referenced in the graph above is used in a TAD CD player.
I think your phase noise graph is very valuable because you seem to have made those measurements by yourself!
May I ask you some questions to you?
1. Which device do you use, Agilent E5505A?
2. Do you measure a phase noise in an electromagnetic dark room?
3. How does a power supply quality connected to the oscillators affect on resultant data?
4. Is it possible to measure phase noise of actual I2S SCK or WS signal in a digital audio circuit?
5. The "Jitter" you referred in your post must be a "Phase Jitter". Can you also measure "Period Jitter" by using other suitable instruments such as Teledyne LeCroy digital oscilloscopes and compare those two jitter values?
Please feel free to ignore my complicated and detailed questions above.
Eventually NDK released an easy-reading document that illustrated an importance of low phase noise oscillators in consumer audio applications, today on their website. The document is written in Japanese only. However, you can look at a figuare of phase noise plots of their typical products.
The title in Kanji characters means "Phase Noise Comparison of Crystal Oscillators".
The OCXO type referenced in the graph above is used in a TAD CD player.
😱the famous CCHD-957 22.5792MHz is only -97dBc at 10Hz
NZ2520SD is -113dBc at 10Hz! and at half price only!
definitely won a try, the best oscillator for audio is redefined
I hope 98.304M and 90.3168M of NZ2520SD will also be available soon
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Your hope will not be likely to be fulfilled.
They say the technology used in NZ2520SD product can not cover near 100 MHz range. Even in the case of Crystek, CCHD-950 and CCHD-957 cover different frequency ranges.
My recent speculation is;
a design of electronic circuit that leads an output signal of those oscillators is far more important than a phase noise profile of original crystal oscillators.
Hi Bunpei.
Answer to above:
1) An old P/N meter from Aeroflex PN9000 was used.
2) No.. I do the testing in a normal "office" lab
3) This test is not so critical as first expected. I use a Linear Lab supply and local decoupling close to the osc (100nF//47-220uF)
4) Very interesting question. I have never done this before, but will give it a try next week and return with a PM.
5) No.. :-(
yes, do not forget to buy NDKs from Shenzen per your earlier undocumented posts, thus attacking other USB to I2S products (like WaveIO?) that is using NDKs for two years in a row. Seems that you still have to learn the difference between quality and $hitty marketing goals! Yes, to place NDKs in your product but it will not do anything good to your "DXIO" (BTW, why IO at the end?... from infinite numbers of names that you could use...) as long as your pretious XMOS processor will resample the external clock source to 400 MHz internal one. This issue was already debated here:
http://www.diyaudio.com/forums/digi...pdif-converter-24bit-96khz-2.html#post2921904
I was in error too about XMOS and how those chips are working but seems that "this issue" is part of their architecture which I doubt is changed with new processors! BTW, stop trying to do anything in software as long as the hardware side (at which you do not have any access) is not cooperating. After all, qusp is right about XMOS in general and your poorly made product in special (layout, decoupling, switching mode PSUs?). My 2 cents..
Please visit to Shenzhen and many China industrial area and you can understand. Even US military buy fakes.
BBC News - China fake parts 'used in US military equipment'
I agree - it is not reasonable to put low phase noise xo in this XMOS if XMOS use dc converter, and even for small, thick, 2 side pcb. Better to add isolator for this design. It can make the vocal more smoother.
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Do you have more information about 3) power supply. What is model number or spec or somethings ? Thank you !
Thank you for your link! I also found that the xmos datasheet has information about SPDIF are reclocked with a flipflop for better timing.
I am sorry if the NDK comment have offensive anyone, it's only based on my poor experience when trying to source quality components, actually I only know the famous TPA buffalo is using crystek.
The current PCB is following the demo circuit and layout in xmos datasheet to achieve the highest c/p ratio and fastest available time.
I totally agree that there are many things can be improved, and there are already many suggestion from other diyer in this post! You are welcome to give more.
A 98M/90M oscillator design with xmos is on progress and reclock with the 98M/90M to the I2S line is also on the next to-do list😀
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