New XMOS usb 384khz

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First one is a basic double sided PCB, basic routing, nothing special. Second one cant see any details because of the white solder resist everywhere, but looks slightly better.
Marketing the same for both.
For best quality I would expect at least a 4 layer board...To put it into perspective I have just done a little camera board for a car reversing camera, 10 layers, every signal layer internal and surrounded by ground planes top and bottom.
 

Hugh Jazz

Banned
2013-02-15 5:19 am
MCLK output = 24.5 and 22.5 MHz for both.

CM has two xo, so xo is always integer of mclk. Good !

XMOS XO is 48Mhz and it is not integer of mclk. Maybe CM can be better on this but maybe XMOS is better for other factor, for example, firmware, driver, etc.

I know CM is very good but I don't know XMOS.
 
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MCLK output = 24.5 and 22.5 MHz for both.

CM has two xo, so xo is always integer of mclk. Good !

XMOS XO is 48Mhz and it is not integer of mclk. Maybe CM can be better on this but maybe XMOS is better for other factor, for example, firmware, driver, etc.

I know CM is very good but I don't know XMOS.


Both chips need a clock to run on (CM looks to be 12MHz, XMOS with be 12, 24, 48 etc) this will be a USB rate multiplier.

Assuming Async operation, this has nothing to do with the master clock. Both chips will take two clock inputs for async mode (one for 44.1.. and one for 48...)
 
xmos has huge amounts of jitter on BLCK/SDATA/LRCK, we are talking about >ns range and this board makes no attempt to clean it up. as es9018 uses its own mclk normally, the incoming blck jitter can have significant effects. I would go with the CM if I had to chose between the 2

why does he always put decoupling caps so far away?

4) No Via in active circuit (via inductance always create jitter problem)
hmm I would be interested to see how longer non impedance controlled and yes..inductive traces compare to the inductance caused by directly connecting with a micro via.
pure marketing.
 
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Hugh Jazz

Banned
2013-02-15 5:19 am
Thank you. So no integer problem. Maybe this is better than CM ... What XMOS chip is this using ? I cannot read device markings.

Datasheets and xCORE Device Part Marking List here -

Xcore | XMOS

EDIT - from hifiduino - thank you.

https://www.xmos.com/download/final...40f0b824d56e19ff74e975c8be&px-time=1365711726

and

http://hifiduino.wordpress.com/2013/04/11/diyinhk-xmos-usb-the-dxio/

I guess XS1-U6-64. 64K.

https://www.xmos.com/download/final...53bd22dcfe8c2ddb231548525d&px-time=1365823013

or 128K U8 ?

https://www.xmos.com/download/final...8836b894505c6a9cd6f4283775&px-time=1365823174

But I hope 128K 1000MIPS on XS1-U10-128. :)

https://www.xmos.com/download/final...dfba98e1ab33089f67a4099352&px-time=1365823079
 
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that depends very much on the DAC, the ESS for example may not even use the MCLK from the usb board and bck is the most important input, it does have a significant effect with ESS even though it reclocks, especially bck that has 400x higher jitter than its own reference clock, thats more than a clock tick and on the reference design no less. 44.1x has even worse jitter, up to 2ns. also some DACs will use bck for the main clock, like TDA. this jitter is 30 times worse than a decent spdif.
 
If the DAC re-clocks, then it will have no effect. The MCLK is the clock the DAC internally runs on, all digital inputs are sampled on this.

A DAC would not use the BCLK when MCLK is available. If you are using a DAC that does not take an MCLK but internally generates based on LR on BCLK (via a PLL or similar) then perhaps this is an issue, but the product is probably "low-end" anyway.
 
clearly you havent worked with ESS dacs very much. if the jitter on bck is more than a clock tick, and LRCK is at a different but still high amount of jitter due to the different speed it runs at, then error can happen. I repeat, other than MCK, the jitter on BCK is the most important and DOES have an effect on the output once it gets to a certain level. if you think that reclocking without buffering is a perfect system, then you are mistaken.

I think a lot of TDA1541A dac owners might disagree that their dacs are low end. in fact anything that doesnt have a reclocking stage will possibly have some problem with a design that outputs bck with more jitter than a tick of its master clock and a different amount on the other inputs. that sort of error is not cleaned up, whether or not its audible will depend on the situation I guess, but its not what I would call great design thats in keeping with the quality of parts that came long before it, or the parts its being used with.

there is also at least one dac here on the forum that uses BCK and MCK tied together as MCK on a modified PCM1794A dac that is considered hi-end, no local master clock at all, guess what USB interface is recommended for it?

1-2ns of jitter is huge, its orders of magnitude higher than spdif interfaces that have been around for decades. other implementations than the reference design may have even worse performance and some may fix by reclocking the XMOS output with the clean master clock. I dont know about you, but I dont feel that running something with such large jitter just because it does hirez is a great trade-off

basically IMO the xmos stuff needs a reclocking stage/buffer on the output, at least the last chips, maybe the new parts are better.
 
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