I love the Chinese $500 dual mono ES9038PRO with NE5532 op amps in the I/V stage (minimum 10mA short circuit output current). The ES9038PRO puts over 30mA per channel at FS and they run 4 channels in parallel on an op amp. I'm sure some people feel it has a positive effect on SQ.
No, and there won't be any, since nobody will bother to do on chip measurements for an audio DAC. But if the jiteratti team would understand that not even FPGAs built in a 7nm 20GHz+ process (and costing north of 10-20k) can guarantee absolute clock synchronization across all chip areas (and therefore the silicon compiler needs to optimize the placement of high speed blocks) then they would accept that an audio chip costing dollars a pop to manufacture will do only so much. I am not holding my breath waiting this to happen, after all a religion is much easier to assimilate than science.
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Dont worry, there will be jitter/PN measurements for andrea's DAC+front end in coming months, more 3rd party measurements from Joseph K will probably be needed for sceptics to accept any result.
Perhaps the skeptism does not lie in the numbers but in whether they make any difference at all beyond a certain point.
Interesting, as a packaging expert once told me the limit was about 2 A. It surprised me that the number was so high. It didn't actually matter much, as the electromigration limit for the I/O cells was way lower anyway.
Nonetheless they aren't used much in low-power integrated circuit design. In my previous job I designed parts of integrated circuits for many different companies; no power electronics, all in the 1 uA to 500 mA supply current range. None used thick aluminium bondwires. One project included an external power MOSFET, that did use thick aluminium bondwires (many in parallel for the source and a single one for the gate).
Regarding the sheet resistance of diffused layers, not sure where you got the "15 ohm per square" value for diffused layers. In fact, if this would be some sort of limit, bipolar transistors could not be built. The minimum sheet resistivity is orders of magnitude lower, check out the tables in https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nbsspecialpublication400-64.pdf
Just a typical value for a CMOS process I've worked in a lot, no intention to suggest it's a physical limit. The point is that it would be silly not to use the metal layers, preferably thick metal layers, when you want to make a 0.2 ohm connection on chip.
Or it can be flat wrong, due to not understanding the underlying functionality of the measuring tool. Ian's comments about the Timepod front end LPF filter, which obscures the phase noise differences between sine and square waves (something I have myself mentioned several times) is a glaring example. Leading to the wrong conclusion that a sine/square converter, a clock buffer or a clock divider has very little additive phase noise/jitter (in the sine oscillator range).
Can't wait for the the Italian partners to jump in and start throwing brown matter in the fan.
Can't wait for the the Italian partners to jump in and start throwing brown matter in the fan.
You would use a "thick metal layer" if a) you have it in the process (unlikely, most modern processes are using now very thin copper or alloys/sandwiches metal layers, gone are the times of 1um aluminum) and b) you can use it, which is not obvious (this may be a tough constraint for the chip layout).
Here you go. I did not name any names (interesting you just jumped in, though) but of course, I should say "DIY partner".
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Sorry, wrong term, meant independent not 3rd party, which you have confirmed now.
Most CMOS processes nowadays have at least eight metal layers of which the upper few are much thicker than the lower ones. You would normally use those upper layers for power, ground and anything that needs to have a low resistance.