OK Marcel - 2 boards on their way here and I will pass one of them off to you for trails. Can I use rePhase to make a filter I'd like to have? - how are filter defined - purely in math/code? The one you showed above is fine... no problem with it whatsoever - just wondered...
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I never heard of rePhase, but if you can generate a .coe file with it, you can load that into the FIR filter with the Xilinx ISE FIR compiler before running synthesis and implementation. The .coe file of a FIR filter is just a text file with a radix definition (like radix = 10 for decimal numbers) and a bunch of coefficients that define the impulse response.
In fact you can make a .coe file with several coefficient sets and tell the FIR compiler that there are several coefficient sets. The FIR filter will then get selection inputs that can be connected to FPGA inputs, so you can choose on the fly between the sets.
Mind you, I intend to combine the last decimation stage (decimation from 352.8 kHz to 88.2 kHz) and the CIC filter roll-off compensation into one FIR filter to reduce the required hardware and the number of rounding steps. The coefficients you would like to have then have to be convolved with those of the CIC filter roll-off compensation. I use a simple home-made Pascal program for that.
By the way, a CIC filter is a very basic linear-phase FIR filter that is extremely hardware efficient, but it can only have a very smooth roll-off. It's basically a clever way to make a cascade of moving average filters. It's often used for the first decimation steps in a decimation chain.
In fact you can make a .coe file with several coefficient sets and tell the FIR compiler that there are several coefficient sets. The FIR filter will then get selection inputs that can be connected to FPGA inputs, so you can choose on the fly between the sets.
Mind you, I intend to combine the last decimation stage (decimation from 352.8 kHz to 88.2 kHz) and the CIC filter roll-off compensation into one FIR filter to reduce the required hardware and the number of rounding steps. The coefficients you would like to have then have to be convolved with those of the CIC filter roll-off compensation. I use a simple home-made Pascal program for that.
By the way, a CIC filter is a very basic linear-phase FIR filter that is extremely hardware efficient, but it can only have a very smooth roll-off. It's basically a clever way to make a cascade of moving average filters. It's often used for the first decimation steps in a decimation chain.
When I read your answer I feel I should probably best stay out of the filter realisation discussion 🙂
I will be very satisfied if it has the shape (FR/phase) we discussed above and really low distorsion.
But maybe the prioritised characteristics is to have the stop band pushed downwards a low as absolutely possible above Fs/2...
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I will be very satisfied if it has the shape (FR/phase) we discussed above and really low distorsion.
But maybe the prioritised characteristics is to have the stop band pushed downwards a low as absolutely possible above Fs/2...
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Well, ideally I would only like to do attenuation (bit shifts in the DAV + splitting the recording into "tracks" - thas all really. I'm nor so sure about its filtering quality as it relies on plugins from Apple etc...
So maybe a good HP would be nice to have!?
I plan to do any needed resampling with Sopran which seem to offer very high quality re-sampling... if not the best - despite that I have to resort to my PC laptop or my Virtualbox emulator... 🙁
Sopran:
Tolvan Data
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If you happen to have a multichannel oscilloscope, could you check if the bits MOD6 and MOD5 tend to be in phase or in antiphase at low audio levels? I'd like to know if the modulator output signal is two's complement or offset binary coded.
I meant an oscilloscope with more than one channel, two is already enough to monitor bits 6 and 5.
I do have one but I'm nor currently at the same location as the EVM and the scope 🙂 I'll do this as soon as I can but it can take a few days.
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That's fine, I only need to know it by the time I'm almost finished, which won't be soon. It's a matter of adding one extra inverter in the Verilog code if it is offset binary.
Batteries, capsules and more components slowly arriving 🙂
And I'm sure there are things missing. Like a case for the EVM and one for batteries etc... quite some way to go and the rockiest remain.. 🙂 maybe a little round circuit board after all...
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And I'm sure there are things missing. Like a case for the EVM and one for batteries etc... quite some way to go and the rockiest remain.. 🙂 maybe a little round circuit board after all...
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Regarding decimation and offset suppression, I haven't worked out the details yet, but I'm pretty sure there are enough FPGA resources left to make a second-order Butterworth IIR high-pass at about 1 Hz by means of an extra feedback loop around the dithered rounding stage. That dithered rounding stage is needed anyway to reduce the word length from sixty-something bits to 24 bits. An IIR filter needs rounding to keep its wordlengths finite, so it makes sense to combine them and keep the total number of rounding stages as small as possible.
In fact I was thinking about something that you can switch between first order, second-order Butterworth and an autocalibration mode where it filters for a few seconds and then freezes, so you just get a fixed offset correction from that moment onwards.
Wow - thats sounds high-tech 🙂 Like it!!!
Transparency... thats all I need 🙂
Got 3pcs 18v 4AH batteries for 5€ each from Amazon.se Charger was 25 :-/
Now to get some sort of connector to these....
They came charged to 18,4V
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Transparency... thats all I need 🙂
Got 3pcs 18v 4AH batteries for 5€ each from Amazon.se Charger was 25 :-/
Now to get some sort of connector to these....
They came charged to 18,4V
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Re HP filtering...
Is it a question about either capacitor coupled inlets or an IIR? If I have caps, can I skip the IIR? If one can skip the IIR in place of caps, I might like a mode with no IIR/HP at all. To have some options and way to evaluate...
I'm perfectly OK with -1dB at 10 Hz... but maybe only -0,1 at 20 🙂
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Is it a question about either capacitor coupled inlets or an IIR? If I have caps, can I skip the IIR? If one can skip the IIR in place of caps, I might like a mode with no IIR/HP at all. To have some options and way to evaluate...
I'm perfectly OK with -1dB at 10 Hz... but maybe only -0,1 at 20 🙂
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The autocalibration mode I have in mind would give you no high-pass at all except for the first few seconds. After those seconds it just adds or subtracts a constant. So just activate it a few seconds before whatever you want to record starts.
With the circuit with the modified evaluation board, you need hundreds of microfarads for AC coupling with only 0.1 dB of roll-off at 20 Hz, but with the circuits based on noninverting amplifiers like Scott's circuits, much smaller values can be used. In either case, an AC coupling cap or other type of analogue high-pass filter will not suppress the offset of the ADC itself.
With the circuit with the modified evaluation board, you need hundreds of microfarads for AC coupling with only 0.1 dB of roll-off at 20 Hz, but with the circuits based on noninverting amplifiers like Scott's circuits, much smaller values can be used. In either case, an AC coupling cap or other type of analogue high-pass filter will not suppress the offset of the ADC itself.
OK thanks - your auto-calibration idea sounds marvellous!! "No high pass at all" - much appreciated. Fantastic actually!
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Regulators arriving tomorrow from ldovr.com.
This series is interesting and this post mention noise and dynamic headroom. Its by the B&O tonmeister...
“High-Res” Audio: Part 12: Outputs – earfluff and eyecandy
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This series is interesting and this post mention noise and dynamic headroom. Its by the B&O tonmeister...
“High-Res” Audio: Part 12: Outputs – earfluff and eyecandy
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